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LAN91C96 Datasheet(PDF) 3 Page - SMSC Corporation

Part # LAN91C96
Description  Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Download  125 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LAN91C96 Datasheet(HTML) 3 Page - SMSC Corporation

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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
SMSC LAN91C965v&3v
Page 3
Rev. 03-28-07
DATASHEET
TABLE OF CONTENTS
Chapter 1
General Description _________________________________________________________________________ 6
Chapter 2
Overview __________________________________________________________________________________ 7
Chapter 3
Pin Configurations_________________________________________________________________________ 10
3.1
Local Bus vs. PCMCIA vs. 68000 Pin Requirements ________________________________________________ 14
Chapter 4
Description of Pin Functions ________________________________________________________________ 16
4.1
Buffer Symbols _______________________________________________________________________________ 20
Chapter 5
Functional Description _____________________________________________________________________ 22
5.1
Buffer Memory _______________________________________________________________________________ 23
5.2
Interrupt Structure____________________________________________________________________________ 30
5.3
Reset Logic___________________________________________________________________________________ 31
5.4
Power Down Logic States_______________________________________________________________________ 31
5.5
LAN91C96 Power Down States __________________________________________________________________ 32
5.6
PCMCIA CONFIGURATION REGISTERS DESCRIPTION ________________________________________ 35
Chapter 6
Frame Format in Buffer Memory for Ethernet __________________________________________________ 37
Chapter 7
Registers Map in I/O Space __________________________________________________________________ 41
7.1
I/O Space Access ______________________________________________________________________________ 41
7.2
I/O Space Registers Description _________________________________________________________________ 41
Chapter 8
Theory of Operation________________________________________________________________________ 65
8.1
Typical Flow of Events for Transmit (Auto Release = 0) _____________________________________________ 67
8.2
Typical Flow of Events for Transmit (Auto Release = 1) _____________________________________________ 68
8.3
Flow of Events for Receive ______________________________________________________________________ 69
Chapter 9
Functional Description of the Blocks __________________________________________________________ 79
9.1
Memory Management Unit _____________________________________________________________________ 79
9.2
Arbiter ______________________________________________________________________________________ 79
9.3
Bus Interface _________________________________________________________________________________ 80
9.4
Wait State Policy ______________________________________________________________________________ 80
9.5
Arbitration Considerations _____________________________________________________________________ 81
9.6
DMA Block __________________________________________________________________________________ 81
9.7
Packet Number FIFOS _________________________________________________________________________ 82
9.8
CSMA Block _________________________________________________________________________________ 84
9.9
Network Interface _____________________________________________________________________________ 85
9.10
10Base-T___________________________________________________________________________________ 86
9.11
AUI _______________________________________________________________________________________ 86
9.12
Physical Interface ___________________________________________________________________________ 86
9.13
Transmit Functions__________________________________________________________________________ 86
9.13.1
Manchester Encoding _______________________________________________________________________ 86
9.13.2
Transmit Drivers ___________________________________________________________________________ 87
9.13.3
Jabber Function____________________________________________________________________________ 87


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