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LAN83C180 Datasheet(PDF) 9 Page - SMSC Corporation |
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LAN83C180 Datasheet(HTML) 9 Page - SMSC Corporation |
9 / 22 page SMSC DS – LAN83C180 Page 9 Rev. 08/24/2001 the reference until the equalizer has adjusted, then it requires up to 1ms to phase lock to the incoming signal. No data is passed to the MII interface until lock is established. RX100 SIPO, Decoder and Descrambler The RX100 SIPO, Decoder and descrambler convert the received signal from serial MLT3 to 4-bit wide parallel receive data on the MII. This appears on the RXD[3:0] bus which is clocked out on the rising edge of RX_CLK. When a frame starts the LAN83C180 decodes the SSD symbols and then asserts the RX_DV signal, in order to inform the MAC that valid data is available. When the LAN83C180 detects the ESD, it deasserts the RX_DV signal. RX100 Latency The latency from the first bit of the “J” symbol on the cable to CRS assertion is between 11 and 15BT. The latency from the first bit of the “T” symbol on the cable to CRS de-assertion is between 19 and 23BT. 100Mb/s Transmit Errors If the LAN83C180 detects that the TX_ER signal has gone active while the TX_EN signal is active, then it will propagate the detected error onto the cable by transmitting the symbol “00100”. Table 1 shows the meaning of the different states of TX_EN and TX_ER. TX_ER is sampled inside the LAN83C180 on the rising edge of TX_CLK. Table 1 - 100MB/S Transmit Error States TX_EN TX_ER TXD [3:0] INDICATION 0 X Ignored Normal Inter Frame Data 1 0 0000 Through 1111 Normal Data Transmission 1 1 0000 Through 1111 Transmit Error Propagation 100Mb/s Receive Errors When there is no data on the cable, the receiver will see only the idle code of scrambled 1’s. If a non idle symbol is detected, the receiver looks for the SSD so that it can align the incoming message for decoding. If any 2 non consecutive zeros are detected within 10 bits, but are not the SSD symbols a false carrier indication is signaled to the MII by asserting RX_ER and setting RXD[3:0] to 1110 while keeping RX_DV inactive. The remainder of the message is ignored until 10 bits of 1’s are detected. If any data is decoded after a SSD which is neither a valid data code nor an ESD, then an error is flagged by setting RX_ER active while the RX_DV signal is active. This also happens if 2 idle codes are detected before a valid ESD has been received –or- descramble synchronization is lost during packet reception. The states of RX_DV and RX_ER are summarized in Table 2. RX_ER is clocked on the falling edge of RX_CLK, and will remain active for at least 1 period of RX_CLK. Table 2 - 100MB/S Receive Error States RX_DV RX_ER RXD [3:0] INDICATION 0 0 0000 Through 1111 Normal Inter Frame 0 1 1110 False Carrier Indication 1 0 0000 Through 1111 Normal Data Reception 1 1 0101 or 0110 Data Reception With Errors |
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Similar Description - LAN83C180 |
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