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LPC47S457-NC Datasheet(PDF) 3 Page - SMSC Corporation |
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LPC47S457-NC Datasheet(HTML) 3 Page - SMSC Corporation |
3 / 259 page SMSC LPC47S45x Page 3 of 259 Rev. 06-01-06 DATASHEET TABLE OF CONTENTS 1 GENERAL DESCRIPTION .................................................................................................................... 9 2 PIN CONFIGURATION ........................................................................................................................ 10 3 PINOUT ................................................................................................................................................ 11 4 PIN DESCRIPTION .............................................................................................................................. 12 4.1 BUFFER TYPE DESCRIPTIONS ............................................................................................................................17 4.2 PINS THAT REQUIRE EXTERNAL PULLUP RESISTORS............................................................................................18 5 DESCRIPTION OF POWER SOURCES AND CLOCK INPUT/OUTPUTS......................................... 19 5.1 3.3 VOLT OPERATION / 5 VOLT TOLERANCE ........................................................................................................19 5.2 POWER FUNCTIONALITY ....................................................................................................................................19 5.2.1 VCC Power.............................................................................................................................................19 5.2.2 VTR Support...........................................................................................................................................19 5.2.3 Vbat Input ...............................................................................................................................................19 5.3 INTERNAL PWRGOOD.....................................................................................................................................20 5.4 32.768 KHZ TRICKLE CLOCK INPUT...................................................................................................................20 5.5 INDICATION OF 32KHZ CLOCK ...........................................................................................................................20 5.6 XOSEL...........................................................................................................................................................21 5.7 TRICKLE POWER FUNCTIONALITY .......................................................................................................................21 5.8 40MHZ CLOCK OUTPUT....................................................................................................................................23 5.9 MAXIMUM CURRENT VALUES .............................................................................................................................23 5.10 POWER MANAGEMENT EVENTS (PME/SCI) ....................................................................................................23 6 FUNCTIONAL DESCRIPTION............................................................................................................. 24 6.1 SUPER I/O REGISTERS......................................................................................................................................24 6.2 HOST PROCESSOR INTERFACE (LPC) ................................................................................................................24 6.3 LPC INTERFACE ...............................................................................................................................................24 6.3.1 LPC Interface Signal Definition...............................................................................................................25 6.3.2 Power Management................................................................................................................................26 6.3.3 LPC Transfers ........................................................................................................................................27 6.4 FLOPPY DISK CONTROLLER ...............................................................................................................................28 6.4.1 FDC Internal Registers ...........................................................................................................................28 6.4.2 Status Register Encoding .......................................................................................................................38 6.4.3 DMA Transfers........................................................................................................................................41 6.4.4 Controller Phases ...................................................................................................................................41 6.4.5 Command Set/Descriptions ....................................................................................................................42 6.4.6 Instruction Set.........................................................................................................................................45 6.4.7 Data Transfer Commands ......................................................................................................................51 6.4.8 Control Commands.................................................................................................................................57 6.4.9 Direct Support for Two Floppy Drives .....................................................................................................62 6.5 SERIAL PORT (UART) ......................................................................................................................................63 6.5.1 Register Description ...............................................................................................................................63 6.5.2 Programmable Baud Rate Generator (AND Divisor Latches DLH, DLL) ................................................70 6.5.3 Effect Of The Reset on Register File ......................................................................................................70 6.5.4 FIFO Interrupt Mode Operation ..............................................................................................................70 6.5.5 FIFO Polled Mode Opertion....................................................................................................................71 6.5.6 Notes On Serial Port Operation ..............................................................................................................75 6.6 INFRARED INTERFACE........................................................................................................................................76 6.6.1 IR Transmit Pin.......................................................................................................................................76 6.7 PARALLEL PORT ...............................................................................................................................................77 6.7.1 IBM XT/AT Compatible, Bi-Directional And EPP Modes........................................................................78 6.7.2 EPP 1.9 Operation..................................................................................................................................80 6.7.3 EPP 1.7 Operation..................................................................................................................................81 6.7.4 Extended Capabilities Parallel Port.........................................................................................................83 6.7.5 Vocabulary..............................................................................................................................................83 6.7.6 ECP Implementation Standard ...............................................................................................................83 |
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