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EMC6D103S Datasheet(PDF) 53 Page - SMSC Corporation |
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EMC6D103S Datasheet(HTML) 53 Page - SMSC Corporation |
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53 / 84 page  Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet SMSC EMC6D103S 53 Revision 0.2 (06-14-06) DATASHEET The Fan Tachometer Reading registers contain the number of 11.111 μs periods (90KHz) between full fan revolutions. Fans produce two tachometer pulses per full revolution. These registers are updated at least once every second. To convert the value in the TACH reading registers to a representative RPM value is a simple mathematical exercise. The 16bit reading is first converted to a decimal number and then multiplied by the clock period (11.11 μs). This gives the measured period of two full TACH pulses which equals 1 full fan revolution. This number is then inverted and multiplied by 60 to give Rotations / minute. For example: If the Tach 1 data bytes contain 0C86h (MSB followed by LSB). This is equivalent to 3206 clock counts. Multiplying this number by 11.111 μs (clock period) yields 0.03562s. This number represents the measured time for two full periods of the TACH signal. Inverting this number and multiplying it by 60 yields a final RPM value of 1684. The larger the returned count, the slower the measured fan speed. The slowest fan speed that can be stored is approximately 82RPM with an output code of FFFDh. This slow speed is not practical to measure in TACH monitoring Mode 2 (see Table 7.2 on page 44 and Table 7.3 on page 45 for minimum RPM’s measured using Mode 2 and Section 7.1.4.4, "Mode 2 – Monitor Tach input When PWM is ‘ON’," on page 41 for a description of this monitoring mode). This value is represented for each fan in a 16 bit, unsigned number. The Fan Tachometer Reading registers always return an accurate fan tachometer measurement, even when a fan is disabled or non-functional, including when the start bit=0. When one byte of a 16-bit register is read, the other byte latches the current value until it is read, in order to ensure a valid reading. The order is LSB first, MSB second. FFFFh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (This could be triggered by a counter overflow). FFFEh, if the SLOW bit in the corresponding TACHx Option register is set (see Section 8.2.28, "Registers 90h-93h: TachX Option Registers," on page 75 for details), indicates that fan is spinning, but too slowly to be measured at the current TACH settings. These registers are read only – a write to these registers has no effect. 8.2.4 Registers 30-32h: Current PWM Duty 2Dh R Tach3 MSB 15 14 13 12 11 10 9 8 N/A 2Eh R Tach4 LSB 7 6 5 4 3 2 1 0 N/A 2Fh R Tach4 MSB 15 14 13 12 11 10 9 8 N/A Table 8.7 Registers 30-32h: Current PWM Duty Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 30h R /W (See Note 8.8) PWM1 Current Duty Cycle 7 6 5 4 3 2 1 0 N/A 31h R /W (See Note 8.8) PWM2 Current Duty Cycle 7 6 5 4 3 2 1 0 N/A 32h R /W (See Note 8.8) PWM3 Current Duty Cycle 7 6 5 4 3 2 1 0 N/A Table 8.6 Registers 28-2Fh: Fan Tachometer Reading (continued) Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value |
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