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5962R9676602VYC Datasheet(PDF) 9 Page - Intersil Corporation |
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5962R9676602VYC Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 11 page 9 Figure 7 shows how the HS-81C55/56RH I/O ports might be configured in a typical system. Timer Section The timer is a 14-bit down counter that counts the TIMER IN pulses and provides either a square wave or pulse when terminal count (TC) is reached. The timer has the I/O address XXXXX100 for the low order byte of the register and the I/O address XXXXX101 for the high order byte of the register. (See Figure 5). To program the timer, the COUNT LENGTH REG is loaded first, one byte at a time, by selecting the timer addresses. Bits 0-13 of the high order count register will specify the length of the next count and bits 14-15 of the high order register will specify the timer output mode (see Figure 8). The value loaded into the count length register can have any value from 2H through 3FFH in Bits 0-13. There are four modes to choose from: M2 and M1 define the timer mode, as shown in Figure 9. FIGURE 6. HS-81C55RH AND HS-81C56RH PORT FUNCTION OUTPUT LATCH DQ CLK CLR D Q LATCH CLK STB (1) (2) (3) READ PORT MODE (4) WRITE PORT PA/PB PIN MUX HS-81C55RH AND HS-81C56RH ONE BIT OF PORT A OR PORT B (1) OUTPUT MODE (2) SIMPLE INPUT (3) STROBED INPUT (4) = 1 FOR OUTPUT MODE = 0 FOR INPUT MODE MULTIPLEXER CONTROL NOTES: 1. READ Port = (IO/M = 1)(RD = 0)(CE Active) (Port Address Selected) 2. WRITE Port = (IO/M = 1)(wr = 0)(CE Active) (Port Address Selected) PORT A PORT C PORT B OUTPUT PORT A A INTR (SIGNAL DATA RECEIVED) A BF (SIGNALS DATA READY) A STB (ACKNOWL. DATA RCV’D) B STB (LOAD PORT B LATCH) B BF (SIGNALS BUFFER IS FULL) B INTR (SIGNALS BUFFER READY FOR READING) INPUT TO HS-80C85RH RST INPUT TO/FROM PERIPHERAL INTERFACE TO INPUT PORT (OPTIONAL) TO HS-80C85RH RST INPUT FIGURE 7. EXAMPLE: COMMAND REGISTER = 00111001 M2 M1 T13 T12 T11 T10 T9 T8 76543210 T7 T6 T5 T4 T3 T2 T1 T0 76543210 TIMER MODE MSB OF CNT LENGTH LSB OF CNT LENGTH FIGURE 8. TIMER FORMAT HS-81C55RH, HS-81C56RH |
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