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HEF4731B Datasheet(PDF) 4 Page - NXP Semiconductors

Part No. HEF4731B
Description  Quadruple 64-bit static shift register
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

HEF4731B Datasheet(HTML) 4 Page - NXP Semiconductors

  HEF4731B Datasheet HTML 1Page - NXP Semiconductors HEF4731B Datasheet HTML 2Page - NXP Semiconductors HEF4731B Datasheet HTML 3Page - NXP Semiconductors HEF4731B Datasheet HTML 4Page - NXP Semiconductors  
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January 1995
4
Philips Semiconductors
Product specification
Quadruple 64-bit static shift register
HEF4731B; HEF4731V
LSI
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP
→ O63
5
115
230 ns
132 ns
+ (0,26 ns/pF) CL
HIGH to LOW
10
tPHL
55
110 ns
47 ns
+ (0,16 ns/pF) CL
15
40
80 ns
34 ns
+ (0,11 ns/pF) CL
5
130
260 ns
138 ns
+ (0,45 ns/pF) CL
LOW to HIGH
10
tPLH
65
130 ns
56 ns
+ (0,19 ns/pF) CL
15
45
90 ns
39 ns
+ (0,13 ns/pF) CL
Transition times O63
5
30
60 ns
10 ns
+ (0,40 ns/pF) CL
HIGH to LOW
10
tTHL
12
24 ns
3 ns
+ (0,18 ns/pF) CL
15
10
20 ns
3 ns
+ (0,13 ns/pF) CL
5
40
80 ns
8 ns
+ (0,65 ns/pF) CL
LOW to HIGH
10
tTLH
20
40 ns
5 ns
+ (0,30 ns/pF) CL
15
15
30 ns
5 ns
+ (0,20 ns/pF) CL
Minimum clock
5
200
80
ns
see also waveforms Fig.4
pulse width; HIGH
10
tWCPH
75
30
ns
15
50
20
ns
Set-up time
5
25
−5ns
D
→ CP
10
tsu
15
−5ns
15
15
−5ns
Hold time
5
50
20
ns
D
→ CP
10
thold
30
10
ns
15
20
5
ns
Maximum clock
5
2.25
6
MHz
Note: the maximum
pulse frequency
10
fmax
6
16
MHz
power dissipation has
15
9
25
MHz
to be observed
Fig.4
Waveforms showing
minimum clock pulse
width, set-up and hold
times for D to CP.
Set-up and hold times
are shown as positive
values but may be
specified as negative
values.


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