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HEF4534B Datasheet(PDF) 4 Page - NXP Semiconductors |
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HEF4534B Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 10 page January 1995 4 Philips Semiconductors Product specification Real time 5-decade counter HEF4534B LSI MODE CONTROL FUNCTION TABLE SELECT INPUTS 1ST DECADE OUTPUT CARRY TO 2ND STAGE CARRY TO 4TH STAGE MODE SA SB LL normal count at 9 to 0 transition at 9 to 0 transition 5-decade and display of the 1st decade of the 3rd decade counter L H inhibited input clock input clock test purposes: clock directly into stages 1, 2 and 4 H H inhibited at 4 to 5 transition of the 1st decade at 9 to 0 transition of the 3rd decade 4-decade counter with ÷ 10 and round- off at front end HL display counts: at 7 to 8 transition of the 1st decade at 9 to 0 transition of the 3rd decade 4-decade counter; 1 ⁄2-pence capability 3, 4, 5, 6, 7 = 5 8, 9, 0, 1, 2 = 0 Fig.3 Error detection timing diagram. The skew time is the time difference between the LOW to HIGH transition of CPA and the HIGH to LOW transition of CPE or vice versa (see Fig.4). The skew time is typically proportional to the external capacitor (Cext) connected from Cext1 and Cext2 (pins 1 and 22) to VSS. The error detector will count an error when a positive edge on the counter clock CPA is not succeeded by a negative edge on the error detector clock CPE within a skew time tSK1 (adjustable by Cext1 at pin 1). The same holds for a negative edge at CPE succeeded by a positive on CPA within a skew time tSK2 (adjustable by Cext2 at pin 22). If error detection is not needed, CPE must be either HIGH or LOW and no Cext is applied. For further information see Fig.5. Fig.4 Skew times timing diagram; tWCPA > tSK1; tWCPE > tSK2. |
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Similar Description - HEF4534B |
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