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HM-65262 Datasheet(PDF) 6 Page - Intersil Corporation

Part No. HM-65262
Description  16K x 1 Asynchronous CMOS Static RAM
Download  8 Pages
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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HM-65262 Datasheet(HTML) 6 Page - Intersil Corporation

   
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6
Low Voltage Data Retention
NOTE:
1. In this mode, E rises after W. The address must remain stable whenever both E and W are low.
FIGURE 3. WRITE CYCLE 1: CONTROLLED BY W (LATE WRITE)
NOTE:
1. In this mode, W rises after E. If W falls before E by a time exceeding TWLQZ (Max) TELQX (Min), and rises after E by a time exceeding
TEHQZ (Max) TWHQZ (Min), then Q will remain in the high impedance state throughout the cycle.
FIGURE 4. WRITE CYCLE 2: CONTROLLED BY E (EARLY WRITE)
Timing Waveforms (Continued)
A
(17) TAVWH
(9) TELWH
(12) TWHAX
(10) TWLWH
(11)
(7) TEHQZ
(14) TWHDX
(13) TDVWH
(15) TWLQZ
(4)
TELQX
(16) TWHQX
(8) TAVAX
E
W
D
Q
TAVWL
(8) TAVAX
(20) TAVEH
E
W
D
Q
(21) TELEH
(22) TWLEH
(23) TDVEH
(19) TEHAX
(16) TWHQX
(24)
TEHDX
(4) TELQX
(15) TWLQZ
(7) TEHQZ
A
(18) TAVEL
HM-65262


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