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FPM2750QFN Datasheet(PDF) 2 Page - Filtronic Compound Semiconductors

Part No. FPM2750QFN
Description  LOW NOISE HIGH LINEARITY BALANCED AMPLIFIER MODULE
Download  8 Pages
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Maker  FILTRONIC [Filtronic Compound Semiconductors]
Homepage  http://www.filtronic.co.uk/
Logo FILTRONIC - Filtronic Compound Semiconductors

FPM2750QFN Datasheet(HTML) 2 Page - Filtronic Compound Semiconductors

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Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Tel: +44 (0) 1325 301111
Fax: +44 (0) 1325 306177
Email: sales@filcs.com
Website: www.filtronic.com
2
Datasheet v2.5
FPM2750QFN
ABSOLUTE MAXIMUM RATING (PER TRANSISTOR)1:
Notes:
1.
TAmbient = 22°C unless otherwise noted; exceeding any one of these absolute maximum ratings may
cause permanent damage to the device
2.
RF Input must be further limited if input VSWR > 2.5:1
3.
Total Power Dissipation is defined as: PTOT = PDC + PIN – POUT
where PDC = DC Bias Power, PIN = RF Input Power, POUT = RF Output Power
Total Power Dissipation shall be de-rated above 22
°C as follows:
PTOT = (150 – TCASE ) / ΘJC W
where TCASE = Temperature of the thermal pad on the underside of the package
4.
ΘJC increases linearly from 124°C/W at a TCASE of 22°C to 145°C/W at a TCASE of 145°C
5.
Information on the mounting of QFN style packages for optimum thermal performance is available on
request.
BIASING GUIDELINES:
Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for
additional information.
Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage
supply for depletion-mode devices used in the FPM2750QFN
Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source
bias voltage, and such circuits provide some temperature stabilization for the device. A nominal
value for circuit development is 4
Ω for a 50% of IDSS operating point.
For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. Class A/B
bias of 25-33% offers an optimised solution for NF and OIP3.
PARAMETER
SYMBOL
TEST CONDITIONS
ABSOLUTE MAXIMUM
Drain-Source Voltage
VDS
6V
Gate-Source Voltage
VGS
-3V
Drain-Source Current
IDS
For VDS < 2V
IDSS
Gate Current
IG
Forward or reverse current
7.5mA
RF Input Power (Note 2)
PIN
Under any acceptable bias state
150mW
Channel Operating Temperature
TCH
Under any acceptable bias state
175°C
Storage Temperature
TSTG
Non-Operating Storage
-55°C to 150°C
Total Power Dissipation (Note 3)
PTOT
See De-Rating Note below
1W
Gain Compression
Comp.
Under any bias conditions
5dB


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