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SVG-2066 Datasheet(PDF) 4 Page - SIRENZA MICRODEVICES |
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SVG-2066 Datasheet(HTML) 4 Page - SIRENZA MICRODEVICES |
4 / 12 page 303 South Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC http://www.sirenza.com 4 EDS-104432 Rev 3 Advanced Information SVG-2066 500MHz-2200MHz 6-Bit VGA Pin Out Description Pin # Label Description 2,3,20,26,28 N/C These are unused pins and not wired inside the package. May be grounded or connected to adjacent pins. 1,7,8,10,16, 21,23,24,25,30 GND Pins are internally grounded 4 RFIN RF input pin. Connects to 100pF cap inside package. 5 J1 Jumper this pin on the PC board to the attenuator input (ATIN) pin #6. Connects to 100pF cap inside package. 6 ATIN Attenuator input pin 9 P8 Parallel interface attenuation control bit 8 dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. 11 P4 Parallel interface attenuation control bit 4 dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. 12 P2 Parallel interface attenuation control bit 2 dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. 13 P1 Parallel interface attenuation control bit 1 dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. 14 P0.5 Parallel interface attenuation control bit 0.5dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. 15 P16 Parallel interface attenuation control bit 16dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. 17 ATOUT Attenuator output pin. 18 J2 Jumper this pin to the attenuator output pin (ATOUT). Connects to 100pF cap inside package. 19 J3 Connect this pin to the amplifier input pin (AMPIN) with the appropriate AMPIN impedance matching 22 AMPIN Amplifier input pin. Internally connected to base of amplifier (~1.3V) 27 RFOUT Amplifier RF output pin. Internally connected to 5V. Not matched to 50 ohm. Use appropriate matching circuit. 29 VCC Power Supply pin to Amplifier. Apply 5.0V to this pin. 31 Data Serial interface data input. 32 CLK Serial interface clock input. 33 LE Latch enable input. Parallel mode can also be latch enabled with this pin. 34, 35 U1 / U2 Parallel mode power-up state logic bits. 0/0 = 0dB, 1/0 = 8dB, 0/1=16dB, 1/1=31dB 36 J5 Jumper this pin to GND on the PC board. Connects to 1000pF cap inside package. 37 J4 Jumper this pin on PC board to VDD pin 38. Connects to 1000pF bypass cap inside package. 38 VDD Power supply pin to Digital Attenuator. Apply 2.7-3.3V to this pin. May be set from another voltage with a voltage divider (pulls 40uA typ, 100uA max) 39 S-P Serial or parallel mode select. Logic low for parallel mode. Logic high for serial mode. 40 VSS Negative supply voltage or GND EPAD GND Exposed area on the bottom side of the package . GND with vias as shown in recommended landing pattern. LE CLK DATA J4 VCC RFOUT RFIN 1 11 31 J1 ATIN GND GND GND GND P0.5 GND P4 P8 P2 P1 P16 21 ATOUT J2 J3 N C AMPIN GND GND N C N C GND U1 U2 S-P VSS VDD J5 GND N C N C GND 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 32 33 34 35 36 37 38 39 40 |
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