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5962F9582301QYC Datasheet(PDF) 7 Page - Intersil Corporation

Part # 5962F9582301QYC
Description  Radiation Hardened 8K x 8 SOS CMOS Static RAM
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

5962F9582301QYC Datasheet(HTML) 7 Page - Intersil Corporation

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7
Test Patterns
MARCH (II) PATTERN
After a background of zeros is written, each cell (from
beginning to end in sequence) is read, written to a one and
reread. When the array is full of ones each cell (from the end
to the beginning) is read, restored to a zero and reread.
After this the pattern is repeated but with complemented
data.
MASEST PATTERN (Multiple Address Select
Pattern)
A checkerboard pattern is written into the memory. Then the
first cell is read, then its binary address complement is read.
The second cell is read and then its binary address
complement is read. This pattern of incrementing the
address and then reading its binary address complement is
repeated until the entire memory is read.
This is then repeated but using a checkerboard bar pattern.
GALROW PATTERN (Row Galloping Pattern)
After a background of zeros is written into the memory a one
is written into the first cell. It is then read alternately with
each other cell in the row. The test cell is then rewritten back
to a zero. The test cell is then incremented and the
sequence is repeated until all cells in the memory have been
used as a test cell.
This is pattern then repeated but using complemented data.
GALCOL PATTERN (Column Galloping Pattern)
After a background of zeros is written into the memory a one
is written into the first cell. It is then read alternately with
each other cell in the column. The test cell is then rewritten
back to a zero. The test cell is then incremented and the
sequence is repeated until all cells in the memory have been
used as a test cell.
This is pattern then repeated but using complemented data.
CHECKERBOARD PATTERN and
CHECKERBOARD BAR
A checkerboard is written (101010) into the memory and
then the pattern is read back. This is then repeated but using
complemented data.
Irradiation Circuit
HS-65647RH (8K x 8 TSOS4 SRAM) 28 LEAD CERAMIC DIP
NOTES:
17. VDD = 5.5V
±0.5V R = 10kΩ±10%.
18. Group E sample size is two die/wafer.
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NC
VDD
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VDD
E2
A8
A9
A11
A10
DQ7
DQ6
DQ5
DQ4
DQ3
W
G
E1
HS-65647RH


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