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AUXILIARY, AGC, AND CONTROL FUNCTIONS

FREQUENCY PLAN

TRF1112

TRF1212

SLWS175A – APRIL 2005 – REVISED DECEMBER 2005

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

External VCO Enable Voltage

CMOS compatible Input. See the

V

Synthesizer #1 (S-Band PLL)

Characteristics table.

Lock Detect Voltage (PLL1)

CMOS compatible Output (active high). See

V

the Synthesizer #1 (S-Band PLL)

Characteristics table.

Lock Detect Voltage (PLL2)

CMOS compatible Output (active high). See

V

the Synthesizer #1 (S-Band PLL)

Characteristics table.

Gain Control Input

0

3

V

Gain Control Output

When loaded with 10-k

Ω load. Output

0

1.5

V

impedance of AGCO is 3.75 k

Ω. Texas

Instruments RF ASICs present a 10-k

Ω load

impedance.

VAGCO Accuracy

±100

mV

Detector Output Voltage

TBD

mV

Detector Accuracy

TBD

mV

Band-Gap Reference Voltage

1.17

V

AGC Time Constant

Set by external loop filter

TBD

µs

EXTLOIP

High

Logic level applied to EXTLOIP and

On-chip VCO1 selection

EXTLOIN pins to select the on-chip VCO

EXTLOIN

High

EXTLOIP

Logic Level applied to EXTLOIP and

Low

Off-chip VCO1 selection

EXTLOIN pins to select the off-chip

EXTLOIN

Low

(external) VCO.

Note: The RFAGC pin on Texas Instruments RF downconverters (such as: TRF1111, TRF1115, or TRF1216)

have an internal load of 10 k

Ω and consequently the user should not add a separate 10-kΩ load resistor.

Table 1. AGCO Voltage vs AGCI Voltage

VAGCI

V

0.0

0.1

0.2

0.3

0.4

0.5

0.6

>0.6

VAGCO

V

1.5

1.2

0.85

0.55

0.2

0.0

0.0

0.0

The TRF1112 / TRF1212 allow a variety of frequency plans. Figure 2 illustrates the allowable combinations of

first and second IFs. However, due to the fact that the chips feature image-reject mixers, significant changes in

the frequency plan can result in degradation of image rejection. This phenomenon is captured in Figure 3.

In order to maintain maximum image rejection and LO suppression, a recommended frequency plan is: RxIF1 =

480 MHz, RxIF2 = 43.75 MHz.

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