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HEF4086B Datasheet(PDF) 4 Page - NXP Semiconductors

Part No. HEF4086B
Description  4-wide 2-input AND-OR-invert gate
Download  5 Pages
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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HEF4086B Datasheet(HTML) 4 Page - NXP Semiconductors

   
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January 1995
4
Philips Semiconductors
Product specification
4-wide 2-input AND-OR-invert gate
HEF4086B
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
I0 to I7 → O
5
90
180
ns
63 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
30
65
ns
19 ns
+ (0,23 ns/pF) CL
15
20
40
ns
12 ns
+ (0,16 ns/pF) CL
5
80
155
ns
53 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
30
60
ns
19 ns
+ (0,23 ns/pF) CL
15
20
40
ns
12 ns
+ (0,16 ns/pF) CL
I8 → O
5
70
140
ns
43 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
25
55
ns
14 ns
+ (0,23 ns/pF) CL
15
20
40
ns
12 ns
+ (0,16 ns/pF) CL
5
55
115
ns
28 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
20
40
ns
9 ns
+ (0,23 ns/pF) CL
15
15
25
ns
7 ns
+ (0,16 ns/pF) CL
I9 → O
5
55
105
ns
28 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
20
45
ns
9 ns
+ (0,23 ns/pF) CL
15
15
30
ns
7 ns
+ (0,16 ns/pF) CL
5
45
90
ns
18 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
15
35
ns
4 ns
+ (0,23 ns/pF) CL
15
10
25
ns
2 ns
+ (0,16 ns/pF) CL
Output transition times
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
HIGH to LOW
10
tTHL
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
LOW to HIGH
10
tTLH
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
VDD
V
TYPICAL FORMULA FOR P (
µW)
Dynamic power
5
525 fi +∑ (foCL) × VDD2
where
dissipation per
10
2600 fi +∑ (foCL) × VDD2
fi = input freq. (MHz)
package (P)
15
7300 fi +∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (f
oCL) = sum of outputs
VDD = supply voltage (V)


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