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DESCRIPTION/ORDERING INFORMATION (CONTINUED)

14

I/O

Port

4

5

6

7

9

10

11

12

P0

P1

P2

P3

P4

P5

P6

P7

Shift

Register

8 Bit

LP Filter

Interrupt

Logic

Control

Input

Filter

15

Power-On

Reset

Read Pulse

Write Pulse

PCF8574

3

2

1

13

16

8

GND

SDA

SCL

A2

A1

A0

INT

Pin numbers shown are for the DW and N packages.

PCF8574

SCPS068F – JULY 2001 – REVISED OCTOBER 2006

interface [serial clock (SCL), serial data (SDA)].

The device features an 8-bit quasi-bidirectional I/O port (P0–P7), including latched outputs with high-current

drive capability for directly driving LEDs. Each quasi-bidirectional I/O can be used as an input or output without

the use of a data-direction control signal. At power on, the I/Os are high. In this mode, only a current source to

turns on when an output is written high and is switched off by the negative edge of SCL. The I/Os should be

high before being used as inputs.

The PCF8574 provides an open-drain output (INT) that can be connected to the interrupt input of a

microcontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After

to the original setting or data is read from, or written to, the port that generated the interrupt. Resetting occurs in

the read mode at the acknowledge bit after the rising edge of the SCL signal, or in the write mode at the

acknowledge bit after the high-to-low transition of the SCL signal. Interrupts that occur during the acknowledge

clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of

the I/Os after resetting is detected and, after the next rising clock edge, is transmitted as INT. Reading from, or

writing to, another device does not affect the interrupt circuit.

By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data

device.

LOGIC DIAGRAM (POSITIVE LOGIC)

2

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