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PCF8574 Datasheet(PDF) 3 Page - Texas Instruments |
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PCF8574 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 23 page www.ti.com To Interrupt Logic P0−P7 VCC GND CI S D Q FF CI S D Q FF Write Pulse Data From Shift Register Power-On Reset Read Pulse Data to Shift Register 100 µA I2C Interface PCF8574 REMOTE 8-BIT I/O EXPANDER FOR I2C BUS SCPS068F – JULY 2001 – REVISED OCTOBER 2006 SIMPLIFIED SCHEMATIC DIAGRAM OF EACH P-PORT INPUT/OUTPUT I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on the SDA I/O while the SCL input is high. After the start condition, the device address byte is sent, most-significant bit (MSB) first, including the data direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDA I/O during the high of the acknowledge-related clock pulse. The address inputs (A0–A2) of the slave device must not be changed between the start and the stop conditions. The data byte follows the address acknowledge. If the R/W bit is high, the data from this device are the values read from the P port. If the R/W bit is low, the data are from the master, to be output to the P port. The data byte is followed by an acknowledge sent from this device. If other data bytes are sent from the master, following the acknowledge, they are ignored by this device. Data are output only if complete bytes are received and acknowledged. The output data will be valid at time, tpv, after the low-to-high transition of SCL and during the clock cycle for the acknowledge. A stop condition, which is a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the master. Interface Definition BIT BYTE 7 (MSB) 6 5 4 3 2 1 0 (LSB) I2C slave address L H L L A2 A1 A0 R/W I/O data bus P7 P6 P5 P4 P3 P2 P1 P0 3 Submit Documentation Feedback |
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