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PCA9548A

WITH RESET

SCPS143B – OCTOBER 2006 – REVISED MARCH 2007

TERMINAL FUNCTIONS

NO.

SOIC (DW),

NAME

DESCRIPTION

SSOP (DB),

QFN (RGE)

TSSOP (PW), AND

TVSOP (DGV)

1

22

A0

2

23

A1

3

24

RESET

4

1

SD0

5

2

SC0

6

3

SD1

7

4

SC1

8

5

SC2

9

6

SC2

10

7

SD3

11

8

SC3

12

9

GND

Ground

13

10

SD4

14

11

SC4

15

12

SD5

16

13

SC5

17

14

SD6

18

15

SC6

19

16

SD7

20

17

SC7

21

18

A2

22

19

SCL

23

20

SDA

24

21

Supply voltage

connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

the SDA input/output while the SCL input is high (see Figure 1). After the start condition, the device address

byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device

must not be changed between the start and the stop conditions.

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (start or stop) (see Figure 2).

A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 1).

4

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