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HEF4059B Datasheet(PDF) 6 Page - NXP Semiconductors |
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HEF4059B Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 6 page January 1995 6 Philips Semiconductors Product specification Programmable divide-by-n counter HEF4059B LSI AC CHARACTERISTICS VSS =0 V; Tamb =25 °C; input transition times ≤ 20 ns AC CHARACTERISTICS VSS =0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V TYPICAL FORMULA FOR P ( µW) Dynamic power 5 1 100 fi +∑(foCL) × VDD2 where dissipation per 10 5 500 fi +∑(foCL) × VDD2 fi = input freq. (MHz) package (P); n = 3 15 15 000 fi +∑(foCL) × VDD2 fo = output freq. (MHz) 5 500 fi +∑(foCL) × VDD2 CL = load capacitance (pF) n = 1000 10 3 500 fi +∑(foCL) × VDD2 ∑(foCL) = sum of outputs 15 9 000 fi +∑(foCL) × VDD2 VDD = supply voltage (V) VDD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays 5 90 180 ns 78 ns + (0,25 ns/pF) CL CP → O10 tPHL 45 90 ns 40 ns + (0,10 ns/pF) CL HIGH to LOW 15 35 70 ns 32 ns + (0,07 ns/pF) CL 5 100 200 ns 76 ns + (0,48 ns/pF) CL LOW to HIGH 10 tPLH 50 100 ns 40 ns + (0,20 ns/pF) CL 15 40 80 ns 33 ns + (0,15 ns/pF) CL Output transition times 5 30 60 ns 10 ns + (0,40 ns/pF) CL HIGH to LOW 10 tTHL 15 30 ns 6 ns + (0,18 ns/pF) CL 15 10 20 ns 4 ns + (0,13 ns/pF) CL 5 45 90 ns 10 ns + (0,70 ns/pF) CL LOW to HIGH 10 tTLH 25 50 ns 9 ns + (0,33 ns/pF) CL 15 16 32 ns 5 ns + (0,23 ns/pF) CL Maximum clock 5 3,5 7 MHz pulse frequency 10 fmax 7,5 15 MHz 15 10,0 20 MHz |
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