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CDP68HC68A2E Datasheet(PDF) 9 Page - Intersil Corporation |
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CDP68HC68A2E Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 15 page 9 Starting Address Register (SAR) Address/Control: (R/W)0010010 - $12 Read/Write: Yes This register is used to enable conversions in all modes and to set the address of the current channel in the CAR. Prior to, or simultaneously with, enabling conversions, the CAR must be set to a known state via the SAR. Once set, the contents of the CAR determine the first channel to be converted when conversions are enabled - hence the name “Starting Address Register”. The CAR may be jammed with the number of a channel which is not selected in the CSR. After the specified channel is converted, subsequent conversions proceed in ascending order, skipping channels not selected in the CSR. Therefore, jamming the CAR with a non-selected channel number will cause a conversion to be performed on that channel once and only once. After stopping a Mode 2 or 3 conversion (by setting ENC low), the CAR must be jammed to match the channel address prior to initiating Data Register reads. If an Address/Control Byte is sent to begin reads from a Data Register other than the one currently addressed by the CAR, the contents of the Data Register may be corrupted. If the CAR contents are known, single or multiple byte reads can be properly made, by sending a matching Address/Control Byte. Bits 5 and 6 in the SAR are “don’t cares” and can be set to either 0’s or 1’s. The functions of the remaining bits are as follows: B7, ENC The Enable Conversions (ENC) bit is used to synchronously switch on and off the successive approximation A/D converter. When this bit is set high, the appropriate conversion operation (as defined in the MSR) is initiated. Setting the ENC bit low stops the conversion operation. If a channel is being converted when ENC is cleared, the conversion of that channel will com- plete and further conversions will be inhibited. B4, SAE Starting Address Enable (SAE). If the SAR is written to, with the SAE bit high, the CAR is jammed with the value defined by CA2, CA1, and CA0. If SAE is low, the CA2, CA1, and CA0 bits are ignored. B3, CA2 Channel Address, bit 2. When writing to the SAR with SAE high, CA2, CA1, and CA0 form a 3-bit channel address which is used to set the CAR and select the first channel to be converted or read. Reading the SAR returns the previously written values for these three bits. To determine the contents of the CAR a read of the Status Register (SR) must be performed. B2, CA1 Channel Address, bit 1. See discussion under CA2. B1, CA0 Channel Address, bit 0. See discussion under CA2. B0, H/L High/Low. For most applications, the SAR should be written with H/L as a 0. In combination with CA2, CA21, and CA0, this bit is used to select a specific High or Low Data Register. H/L only has significance in 10-bit mode. The 10-bit read sequence is High Data Register followed by Low Data Register for each channel read. When jamming the CAR prior to reads, H/L should be set low, unless the user specifically wants to skip the first High Data Register. When read, this bit, indicates whether the next Data Register read will access the High or Low Data Register. In 8-bit mode, H/L is ignored by the A2. Status Register (SR) Address/Control: 00010011 - $13 Read/Write: Read Only This is a read only register used to monitor the status of the A/D converter. If an Address/Control Byte of $13 is sent to the A2, the Status Register will be addressed and will remain addressed until the CE pin is brought low. This provides efficient polling of the SR by allowing multiple reads of the SR with only one Address/Control Byte transmission. Bits 0 and 4 of the SR are always read as lows. The significance of each of the other bits is: B7, INT Interrupt. In Modes 1 and 2, this bit is set high under the same conditions that the INT pin would be activated (see Conversion Modes). Once set, the INT bit can be cleared by reading the SR, reading any Data Register, or writing to the MSR or CSR. The INT bit is not affected by the state of the IE bit in the MSR. B6, ACC All Conversions Complete bit. When high, this status bit indicates that conversions have been completed on all channels selected in the CSR. It is cleared by reading any of the Data Registers or by writing to the MSR or CSR. In 10-bit mode, ACC = 1 implies that the DV bits of all active channels are true (see Data Registers). This bit is often used in Modes 2 and 3. In Mode 1, ACC will only be set if conversions are explicitly invoked (via writes to the SAR) for each channel selected in the CSR. B5, CIP Conversion In Progress bit. This bit is logically high when a conversion is initiated and goes low when a conversion completes. In the scanning modes, Modes 2 and 3, CIP will go low momen- tarily between successive channels and cannot be used in lieu of ACC in Mode 2. 76543 210 ENC SAE CA2 CA1 CA0 H/L $12 0 0 7654 3210 INT ACC CIP CA2 CA1 CA0 $13 0 0 CDP68HC68A2 |
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