1

TM

Features

• Two Operating Modes

- Mode 0 - Functionally Compatible with Industry

Types Such as the TR1602A and CDP6402

- Mode 1 - Interfaces Directly with CDP1800 Series

Microprocessors without Additional Components

• Full or Half-Duplex Operation

• Parity, Framing, and Overrun Error Detection

• Fully Programmable with Externally Selectable Word

Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and

1, 1-1/2, or 2 Stop Bits

Description

The CDP1854A/3 and CDP1854AC/3 are high reliability

silicon gate CMOS Universal Asynchronous Receiver/Trans-

mitter (UART) circuits. They are designed to provide the

necessary formatting and control for interfacing between

serial and parallel data. For example, these UARTs can be

used to interface between a peripheral or terminal with serial

I/O ports and the 8-bit CDP1800-series microprocessor

parallel data bus system. The CDP1854A/3 is capable of full

duplex operation, i.e., simultaneous conversion of serial

input data to parallel output data and parallel input data to

serial output data.

The CDP1854A/3 UART can be programmed to operate in

one of two modes by using the mode control input. When the

mode input is high (MODE = 1), the CDP1854A/3 is directly

compatible with the CDP1800 series microprocessor system

without additional interface circuitry. When the mode input is

low (MODE = 0), the device is functionally compatible with

industry standard UARTs such as the TR1602A and

CDP6402. It is also pin compatible with these types, except

that pin 2 is used for the mode control input.

The CDP1854A/3 and the CDP1854AC/3 are functionally

identical. The CDP1854A/3 has a recommended operating

voltage range of 4V to 10.5V, and the CDP1854AC/3 has a

recommended operating voltage range of 4V to 6.5V.

Ordering Information

PACK-

AGE

TEMP.

RANGE

5V/200K

BAUD

10V/400K

BAUD

PKG.

NO.

SBDIP

Pinouts

CDP1854A/3, CDP1854AC/3 (SBDIP) (MODE 0)

TOP VIEW

CDP1854A/3, CDP1854AC/3 (SBDIP) (MODE 1)

TOP VIEW

13

1

2

3

4

5

6

7

8

9

10

11

12

14

15

16

17

18

19

20

VDD

RRD

R BUS 7

R BUS 6

R BUS 5

R BUS 4

R BUS 3

R BUS 2

R BUS 1

R BUS 0

PE

FE

OE

SFD

R CLOCK

DAR

DA

SDI

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

T CLOCK

EPE

WLS 1

WLS 2

SBS

PI

CRL

T BUS 7

T BUS 6

T BUS 5

T BUS 4

T BUS 3

T BUS 2

T BUS 1

T BUS 0

SD0

TSRE

THRL

THRE

MR

13

1

2

3

4

5

6

7

8

9

10

11

12

14

15

16

17

18

19

20

CS2

R BUS 7

R BUS 6

R BUS 5

R BUS 4

R BUS 3

R BUS 2

R BUS 1

R BUS 0

INT

FE

PE/OE

RSEL

R CLOCK

TPB

DA

SDI

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

T CLOCK

CTS

ES

PS1

NC

CS3

RD/WR

T BUS 7

T BUS 6

T BUS 5

T BUS 4

T BUS 3

T BUS 2

T BUS 1

T BUS 0

SD0

RTS

CS1

THRE

CLEAR

NC = NO CONNECT

March 1997

CDP1854A/3,

CDP1854AC/3

High Reliability CMOS Programmable Universal

Asynchronous Receiver/Transmitter (UART)

File Number

1715.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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