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HEF4023B Datasheet(PDF) 3 Page - NXP Semiconductors

Part No. HEF4023B
Description  Triple 3-input NAND gate
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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HEF4023B Datasheet(HTML) 3 Page - NXP Semiconductors

   
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January 1995
3
Philips Semiconductors
Product specification
Triple 3-input NAND gate
HEF4023B
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
In → On
5
65
135
ns
38 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
25
50
ns
14 ns
+ (0,23 ns/pF) CL
15
15
30
ns
7 ns
+ (0,16 ns/pF) CL
5
65
130
ns
38 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
30
60
ns
19 ns
+ (0,23 ns/pF) CL
15
25
45
ns
17 ns
+ (0,16 ns/pF) CL
Output transition times
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
HIGH to LOW
10
tTHL
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
LOW to HIGH
10
tTLH
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
VDD
V
TYPICAL FORMULA FOR P (
µW)
Dynamic power
5
1200 fi +∑ (foCL) × VDD2
where
dissipation per
10
5500 fi +∑ (foCL) × VDD2
fi = input freq. (MHz)
package (P)
15
16 400 fi +∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)


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