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HEF4021B Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. HEF4021B
Description  8-bit static shift register
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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HEF4021B Datasheet(HTML) 2 Page - NXP Semiconductors

   
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January 1995
2
Philips Semiconductors
Product specification
8-bit static shift register
HEF4021B
MSI
DESCRIPTION
The HEF4021B is an 8-bit static shift register
(parallel-to-serial converter) with a synchronous serial
data input (DS), a clock input (CP), an asynchronous active
HIGH parallel load input (PL), eight asynchronous parallel
data inputs (P0 to P7) and buffered parallel outputs from
the last three stages (05 to O7).
Each register stage is a D-type master-slave flip-flop with
a set direct/clear direct input. Information on P0 to P7 is
asynchronously loaded into the register while PL is HIGH,
independent of CP and DS. When PL is LOW, data on
DS is shifted into the first register position and all the data
in the register is shifted one position to the right on the
LOW to HIGH transition of CP. Schmitt-trigger action in the
clock input makes the circuit highly tolerant to slower clock
rise and fall times.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
HEF4021BP(N):
16-lead DIL; plastic
(SOT38-1)
HEF4021BD(F):
16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4021BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
PL
parallel load input
P0 to P7
parallel data inputs
DS
serial data input
CP
clock input (LOW to HIGH edge-triggered)
O5 to O7
buffered parallel outputs from the last three stages


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