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GC3021A Datasheet(PDF) 11 Page - Texas Instruments

Part No. GC3021A
Description  3.3V MIXER AND CARRIER REMOVAL CHIP
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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GC3021A Datasheet(HTML) 11 Page - Texas Instruments

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Texas Instruments Incorporated
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GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP
SLWS137A
This document contains information which may be changed at any time without notice
outputs. The snapshot can be programmed to store every sample, every other sample, every third sample,
or every fourth sample. The rate control is primarily used when capturing samples of offset-QPSK data
which is processed by the chip at twice the baud rate. Only every other sample of the offset-QPSK sample
is of interest.
The snapshot can be triggered by the input syncs, the delayed input syncs, the sync counter’s
terminal count or the snap sync input. Once triggered, the snapshot start time can be delayed by up to 256
sample clocks, where the sample clock rate is dependant upon the snapshot rate control.
The snapshot RAM is a read only memory which is read using addresses 256 through 511 of the
control interface. Addresses 256 through 319 read SI, addresses 320 through 383 read SQ, addresses 384
through 447 read ASIN, and addresses 448 through 511 read ACOS. The 12 bit values are sign extended
to 16 bits in the control interface.
2.11
OUTPUT FORMAT
The chip has four 12 bit output ports labeled YA, YB, YC, and YD. Each port can be individually
configured to output mixer results (Ieven, Qeven, Iodd, Qodd), or symbol and NCO samples. The symbol and
NCO samples are the snapshot RAM inputs (SI, SQ, sine, cosine). The output selection is shown in Table
1 below:
The YA, YB, YC and YD outputs can be rounded to 12, 10 or 8 bits and can be masked to a desired
number of bits through the use of four 12 bit mask words. The masks are bitwise ANDed with the output
words to selectively clear the output bits.
Output enable controls are provided to individually turn off these outputs.
2.12
DATA DELAYS
The data delay through the chip in input clock cycles is shown in Table 2 below.
Table 1: OUTPUT SELECTION
OUTPUT
PORT
OUTPUT SELECT
01
YA
Ieven
SI
YB
Qeven
SQ
YC
Iodd
cosine
YD
Qodd
sine
Table 2: DATA DELAYS
FROM
TO
DELAY
MODE
I, Q
SI, SQ
15
OUTSEL=1
I, Q
I, Q (even/odd)
13
OUTSEL=0


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