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GC3021A Datasheet(PDF) 8 Page - Texas Instruments

Part No. GC3021A
Description  3.3V MIXER AND CARRIER REMOVAL CHIP
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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GC3021A Datasheet(HTML) 8 Page - Texas Instruments

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Texas Instruments Incorporated
- 6 -
GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP
SLWS137A
This document contains information which may be changed at any time without notice
Figure 3. The outputs from these adders are saturated to plus or minus full scale (12 bits) if overflow is
detected.
2.6
SYMBOL ALIGN
The symbol align circuit is used in the carrier removal mode to process offset (or staggered) QPSK
signals. The offset is removed by delaying the SI sample by one clock cycle so that it is paired with the next
SQ sample. Every other SI and SQ pair is held for two clock cycles, effectively decimating the sample rate
by two. The symbol offset circuit is controlled by the OFFSET and OFFSET_HOLD control bits described in
Section 4.1 The symbol offset circuit is synchronized by the OFFSET_SYNC described in Section 4.2.
2.7
PHASE ERROR RAM
The the I and Q samples are passed to the phase error RAM. The phase error RAM uses the upper
7 bits of the I and Q values to look up the sign of the phase error for the sample. The phase error RAM
contents are downloaded through the control interface. The phase error RAM outputs a 1 or a 0 depending
upon whether the phase angle of the (I, Q) complex pair is greater than or smaller than the nearest decision
point for the signal’s constellation pattern. A “0” means that the phase angle needs to be increased to match
the decision point and a “1” means it needs to be decreased. A block diagram of the phase error RAM circuit
is shown in Figure 4.
Figure 4. PHASE ERROR RAM
The round circuit rounds the 12 bit I and Q samples into the upper 6 or 7 bits, or, if rounding is
disabled, truncates them. If the quadrant map (Qmap) mode is enabled the circuit rounds to 7 bits, otherwise
it rounds to 6 bits. The rounding is performed using the round to even technique.
The rounded bits are passed to the unsigned magnitude circuit where, if Qmap is enabled, they are
converted from 7 bit 2’s complement signed numbers to 6 bit unsigned numbers. The conversion is
performed using 2’s complement negation unless the invert control is set. If the invert control is set, then the
negation is performed by inverting the data bits (i.e., a 1’s complement negation is used).
If Qmap is enabled the circuit outputs the 6 bit magnitude and the sign bit. If Qmap is turned off the
circuit outputs the 6 bit signed number from the round circuit.
ROUND
UNSIGNED
MAGNITUDE
Q
QMAP_ROUND
Enable
6/7 Bits
Enable
Mode
QMAP_INVERT
12 Bits
7 Bits
6 Bits
sign
QMAP_ENABLE
I
12 Bits
6 Bits
sign
2 MSBs
4 LSBs
256 BY 16
RAM
16 TO 1
MUX
16 Bits
R[0:1]
R[2:7]
C[0:15]
A[0:7]
A8*CS*R/W
W[0:7]
WE
PHASE
ERROR
From
Symbol
Offset
QMAP_ENABLE
ROUND
UNSIGNED
MAGNITUDE
Enable
6/7 Bits
Enable
Mode
7 Bits


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