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GC3021A Datasheet(PDF) 4 Page - Texas Instruments

Part No. GC3021A
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com

GC3021A Datasheet(HTML) 4 Page - Texas Instruments

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Texas Instruments Incorporated
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This document contains information which may be changed at any time without notice
Fabricated in 0.5 micron CMOS technology, the GC3021A chip is designed to mix input data with
an internally generated sine/cosine sequence. The chip can be used as a signal mixer, or if the phase error
lookup and phase lock loop (PLL) circuitry is enabled, as a carrier removal circuit for signal demodulation.
The mixer accepts complex data at rates up to 100 MHz , or real samples at rates up to 200 MHz in the real
input mode . The chip mixes the input with a complex sinusoid, and outputs the results at a 100 MHz rate.
The input data in the real mode is assumed to be even/odd sample pairs. The 200 MHz input data
is split into even and odd samples streams, each at a rate of 100 million samples per second. The even and
odd time sample data streams are mixed with sines and cosines which have also been split into even and
odd time streams. The complex results are then output as two complex pairs at 100 MHz, one for the even
time samples and one for the odd time samples.
The frequency of the sine/cosine sequence is specified as a 32 bit phase word which drives a phase
accumulator. A carry input to the phase accumulator allows the user to extend the tuning resolution with an
external accumulator.
The GC3021A chip’s carrier removal mode allows the chip to be used as part of a QPSK/QAM
demodulator using decision error feed back to achieve carrier lock. A phase error feedback circuit uses the
upper 7 bits of the I and Q mixer outputs to lookup a one bit phase error term. The phase error lookup is
performed by mapping the I/Q pair into a single quadrant so that the lookup table address is only 12 bits (6
bits of I and 6 bits of Q). The 4096 bit lookup table is programmed by the user to output the sign of the phase
error for each possible I/Q pair. This phase error feeds a phase-lock-loop (PLL) circuit which adjusts the
sinusoid frequency to drive the average phase error to zero.
A snapshot RAM is included to store blocks of I/Q symbol outputs and the sine/cosine pairs used
to generate them. This information is used by an external DSP chip or microprocessor to lookup the symbol
error, to rotate the error by the sine/cosine phase, and then update equalizer coefficients.
On chip diagnostic circuits are provided to simplify system debug and maintenance.
The chip receives configuration and control information over a microprocessor compatible bus
consisting of a 16 bit data I/O port, a 9 bit address port, a read enable, a write enable, and a chip enable
strobe. The control registers, coefficient registers, phase error RAM and snapshot memory are mapped into
the 512 word address space of the control port.
A detailed description of the major circuits within the chip follows.
The control interface allows an external processor to configure the chip, to capture and read
samples from the chip and to perform diagnostics.
The chip is configured by writing control information into control registers within the chip. The
registers are written to or read from using the C[0:15], A[0:8], RE, WE, and CE pins. Each control register
has been assigned a unique address within the chip. An external processor (a microprocessor, computer,

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