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SN75173D Datasheet(PDF) 5 Page - Texas Instruments |
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SN75173D Datasheet(HTML) 5 Page - Texas Instruments |
5 / 18 page SN55173, SN65173, SN75173 QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS144E – OCTOBER 1980 – REVISED APRIL 2000 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIT+ Positive-going input threshold voltage VO = 2.7 V, IO = – 0.4 mA 0.2 V VIT– Negative-going input threshold voltage VO = 0.5 V, IO = 16 mA – 0.2‡ V Vhys Hysteresis (VIT+ – VIT–) See Figure 4 50 mV VIK Enable-input clamp voltage II = – 18 mA – 1.5 V SN55173 2.5 V VOH High-level output voltage VID = 200 mV, IOH = – 400 µA SN65173, SN75173 2.7 V VOL Low level output voltage VID = 200 mV See Figure 1 IOL = 8 mA 0.45 V VOL Low-level output voltage VID = – 200 mV, See Figure 1 IOL = 16 mA 0.5 V IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ±20 µA II Line input current Other input at 0 V See Note 3 VI = 12 V 1 mA II Line input current Other input at 0 V, See Note 3 VI = – 7 V – 0.8 mA IIH High-level enable-input current VIH = 2.7 V 20 µA IIL Low-level enable-input current VIL = 0.4 V – 100 µA ri Input resistance 12 k Ω IOS Short-circuit output current –15 –85 mA ICC Supply current Outputs disabled 70 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold voltage levels only. NOTE 3: Refer to TIA/EIA-422-B and TIA/EIA-423-B for exact conditions. switching characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output VID = – 1.5 V to 1.5 V, 20 35 ns tPHL Propagation delay time, high-to-low-level output ID , CL = 15 pF, See Figure 1 22 35 ns tPZH Output enable time to high level CL = 15 pF, See Figure 2 17 22 ns tPZL Output enable time to low level CL = 15 pF, See Figure 3 20 25 ns tPHZ Output disable time from high level CL = 5 pF, See Figure 2 21 30 ns tPLZ Output disable time from low level CL = 5 pF, See Figure 3 30 40 ns |
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