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SN65175DR Datasheet(PDF) 4 Page - Texas Instruments |
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SN65175DR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 16 page SN65175, SN75175 QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS145C − OCTOBER 1990 − REVISED NOVEMBER 2006 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of common-mode input voltage, supply voltage and operating free-air temperature PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIT+ Positive-going input threshold voltage VO = 2.7 V, IO = − 0.4 mA 0.2 V VIT− Negative-going input threshold voltage VO = 0.5 V, IO = 16 mA − 0.2‡ V Vhys Hysteresis voltage (VIT+ − VIT−) See Figure 4 50 mV VIK Enable-input clamp voltage II = − 18 mA − 1.5 V VOH High-level output voltage VID = 200 mV, IOH = − 400 µA, See Figure 1 2.7 V VOL Low-level output voltage VID = − 200 mV, See Figure 1 IOL = 8 mA 0.45 V VOL Low-level output voltage VID = − 200 mV, See Figure 1 IOL = 16 mA 0.5 V IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ±20 µA II Line input current Other input at 0 V, See Note 3 VI = 12 V 1 mA II Line input current Other input at 0 V, See Note 3 VI = − 7 V − 0.8 mA IIH High-level enable-input current VIH = 2.7 V 20 µA IIL Low-level enable-input current VIL = 0.4 V − 100 µA ri Input resistance 12 k Ω IOS Short-circuit output current§ −15 −85 mA ICC Supply current Outputs disabled 70 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold voltage levels only. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 3: Refer to ANSI Standards EIA/TIA-422-B, RS-423-B, and RS-485 for exact conditions. switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low- to high-level output See Figure 2 22 35 ns tPHL Propagation delay time, high- to low-level output See Figure 2 25 35 ns tPZH Output enable time to high level See Figure 3 13 30 ns tPZL Output enable time to low level See Figure 3 19 30 ns tPHZ Output disable time from high level See Figure 3 26 35 ns tPLZ Output disable time from low level See Figure 3 25 35 ns |
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