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HEF4017B Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. HEF4017B
Description  5-stage Johnson counter
Download  8 Pages
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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HEF4017B Datasheet(HTML) 2 Page - NXP Semiconductors

   
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January 1995
2
Philips Semiconductors
Product specification
5-stage Johnson counter
HEF4017B
MSI
DESCRIPTION
The HEF4017B is a 5-stage Johnson decade counter with
ten spike-free decoded active HIGH outputs (Oo to O9), an
active LOW output from the most significant flip-flop (O5-9),
active HIGH and active LOW clock inputs (CP0, CP1) and
an overriding asynchronous master reset input (MR).
The counter is advanced by either a LOW to HIGH
transition at CP0 while CP1 is LOW or a HIGH to LOW
transition at CP1 while CP0 is HIGH (see also function
table).
When cascading counters, the O5-9 output, which is LOW
while the counter is in states 5, 6, 7, 8 and 9, can be used
to drive the CP0 input of the next counter.
A HIGH on MR resets the counter to zero
(Oo = O5-9 = HIGH; O1 to O9 = LOW) independent of the
clock inputs (CP0, CP1).
Automatic code correction of the counter is provided by an
internal circuit: following any illegal code the counter
returns to a proper counting mode within 11 clock pulses.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
HEF4017BP(N):
16-lead DIL; plastic (SOT38-1)
HEF4017BD(F):
16-lead DIL; ceramic (cerdip) (SOT74)
HEF4017BT(D):
16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
CP0
clock input (LOW to HIGH triggered)
CP1
clock input (HIGH to LOW triggered)
MR
master reset input
O0 to O9
decoded outputs
O5-9
carry output (active LOW)


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