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HEF40162B Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. HEF40162B
Description  4-bit synchronous decade counter with synchronous reset
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com

HEF40162B Datasheet(HTML) 2 Page - NXP Semiconductors

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January 1995
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
synchronous reset
The HEF40162B is a fully synchronous edge-triggered
4-bit decade counter with a clock input (CP), four
synchronous parallel data inputs (P0 to P3), four
synchronous mode control inputs (parallel enable (PE),
count enable parallel (CEP), count enable trickle (CET)
and synchronous reset (SR)), buffered outputs from all
four bit positions (O0 to O3) and a terminal count output
Operation is synchronous and occurs on the LOW to HIGH
transition of CP. When PE is LOW, the next LOW to HIGH
transition of CP loads data into the counter from P0 to P3.
When PE is HIGH, the next LOW to HIGH transition of CP
advances the counter to its next state only if both CEP and
CET are HIGH; otherwise no change occurs in the state of
the counter. TC is HIGH when the state of the counter is 9
(O0 = O3 = HIGH, O1 =O2 = LOW) and when CET is
HIGH. A LOW on SR sets all outputs (O0 to O3 and TC)
LOW on the next LOW to HIGH transition of CP,
independent of the state of all other synchronous mode
control inputs (CEP, CET and PE). Multistage
synchronous counting is possible without additional
components by using a carry look-ahead counting
technique; in this case, TC is used to enable successive
cascaded stages. CEP, CET, PE and SR must be stable
only during the set-up time before the LOW to HIGH
transition of CP.
See Family Specifications
Fig.1 Functional diagram.

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