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HEF40160B Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. HEF40160B
Description  4-bit synchronous decade counter with asynchronous reset
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

HEF40160B Datasheet(HTML) 2 Page - NXP Semiconductors

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January 1995
2
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
HEF40160B
MSI
DESCRIPTION
The HEF40160B is a fully synchronous edge-triggered
4-bit decade counter with a clock input (CP), an overriding
asynchronous master reset (MR), four parallel data inputs
(P0 to P3), three synchronous mode control inputs (parallel
enable (PE), count enable parallel (CEP) and count enable
trickle (CET)), buffered outputs from all four bit positions
(O0 to O3) and a terminal count output (TC).
Operation is fully synchronous (except for the MR input)
and occurs on the LOW to HIGH transition of CP. When
PE is LOW, the next LOW to HIGH transition of CP loads
data into the counter from P0 to P3 regardless of the levels
of CEP and CET inputs.
When PE is HIGH, the next LOW to HIGH transition of CP
advances the counter to its next state only if both CEP and
CET are HIGH; otherwise, no change occurs in the state
of the counter. TC is HIGH when the state of the counter is
9 (O0 =O3 = HIGH, O1 =O2 = LOW) and when CET is
HIGH. A LOW on MR sets all outputs (O0 to O3 and TC)
LOW, independent of the state of all other inputs.
Multistage synchronous counting is possible without
additional components by using a carry look-ahead
counting technique; in this case, TC is used to enable
successive cascaded stages. CEP, CET and PE must be
stable only during the set-up time before the LOW to HIGH
transition of CP.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
Fig.1 Functional diagram.


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