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HEF40160B Datasheet(PDF) 6 Page - NXP Semiconductors

Part No. HEF40160B
Description  4-bit synchronous decade counter with asynchronous reset
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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HEF40160B Datasheet(HTML) 6 Page - NXP Semiconductors

 
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January 1995
6
Philips Semiconductors
Product specification
4-bit synchronous decade counter with
asynchronous reset
HEF40160B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
Output transition times
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
HIGH to LOW
10
tTHL
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
LOW to HIGH
10
tTLH
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
VDD
V
SYMBOL
MIN.
TYP.
MAX.
Minimum clock
5
100
50
ns
see also waveforms
Figs 5, 6, 7 and 8
pulse width; LOW
10
tWCPL
40
20
ns
15
30
15
ns
Minimum MR
5
100
50
ns
pulse width; LOW
10
tWMRL
40
20
ns
15
30
15
ns
Recovery time
5
25
0
ns
for MR
10
tRMR
15
0
ns
15
10
0
ns
Set-up times
5
110
55
ns
Pn → CP
10
tsu
40
20
ns
15
30
15
ns
5
120
60
ns
PE
→ CP
10
tsu
40
20
ns
15
25
10
ns
5
260
130
ns
CEP, CET
→ CP
10
tsu
100
50
ns
15
70
35
ns
Hold times
5
20
−35
ns
Pn → CP
10
thold
10
−10
ns
15
5
−10
ns
515
−45
ns
PE
→ CP
10
thold
5
−15
ns
15
5
−10
ns
525
−105
ns
CEP, CET
→ CP
10
thold
15
−35
ns
15
10
−25
ns
VDD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA


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