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HEF4007UB Datasheet(PDF) 2 Page - NXP Semiconductors |
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HEF4007UB Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 8 page January 1995 2 Philips Semiconductors Product specification Dual complementary pair and inverter HEF4007UB gates DESCRIPTION The HEF4007UB is a dual complementary pair and an inverter with access to each device. It has three n-channel and three p-channel enhancement mode MOS transistors. Fig.1 Schematic diagram. HEF4007UBP(N): 14-lead DIL; plastic (SOT27-1) HEF4007UBD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4007UBT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.2 Pinning diagram. PINNING FAMILY DATA, IDD LIMITS category GATES See Family Specifications for VIH/VIL unbuffered stages SP2, SP3 source connections to 2nd and 3rd p-channel transistors DP1, DP2 drain connections from the 1st and 2nd p-channel transistors DN1,DN2 drain connections from the 1st and 2nd n-channel transistors SN2,SN3 source connections to the 2nd and 3rd n-channel transistors DN/P3 common connection to the 3rd p-channel and n-channel transistor drains G1 to G3 gate connections to n-channel and p-channel of the three transistor pairs |
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