Philips Semiconductors

Product specification

FBL22040

3.3V BTL 8-bit TTL to BTL transceiver

1998 Dec 07

3

PIN CONFIGURATION

52 51 50 49 48 47 46

45 44 43 42 41 40

39

38

37

36

35

34

33

32

31

30

29

28

27

1

2

3

4

5

6

7

8

9

10

11

12

13

14 15 16 17 18 19

20

21 22 23 24 25 26

BUS GND

B1

BUS GND

B2

BUS GND

B3

BUS GND

B4

BUS GND

B5

BUS GND

B6

BUS GND

LOGIC GND

AI1

AI2

AO2

LOGIC GND

AO3

LOGIC GND

AI3

AI4

AO4

LOGIC GND

AO5

LOGIC GND

8-Bit Transceiver

52-lead PQFP

FBL22040

SG00114

DESCRIPTION

The FBL22040 is an 8-bit bidirectional BTL transceiver and is

intended to provide the electrical interface to a high performance

wired-OR bus. The FBL22040 is an inverting transceiver.

The B-port drivers are Low-capacitance open collectors with

controlled ramp and are designed to sink 100mA. Precision band

gap references on the B-port insure very good noise margins by

limiting the switching threshold to a narrow region centered at 1.55V.

The B-port interfaces to “Backplane Transceiver Logic” (See the

IEEE 1194.1 BTL standard). BTL features low power consumption

by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced

capacitive loading by placing an internal series diode on the drivers.

BTL also provides incident wave switching, a necessity for high

performance backplanes.

The A-port operates at TTL levels with separate I/O. The 3-state

A-port drivers are enabled when OEA goes High after an extra 6ns

delay which is built in to provide a break-before-make function.

When OEA goes Low, A-port drivers become High impedance

without any extra delay. During power on/off cycles, the A-port

The B-port has two output enables, OEB0 and OEB1. When OEB0

is High and OEB1 is Low the output is enabled. When OEB0 is Low

or if OEB1 is High, the B-port is inactive and is at the level of the

backplane signal.

To support live insertion, OEB0 is held Low during power on/off

cycles to insure glitch free B port drivers. Proper bias for B port

drivers during live insertion is provided by the BIAS V pin when at a

The LOGIC GND and BUS GND pins are isolated in the package to

minimize noise coupling between the BTL and TTL sides. These

pins should be tied to a common ground external to the package.

Each BTL driver has an associated BUS GND pin that acts as a

signal return path and these BUS GND pins are internally isolated

from each other. In the event of a ground return fault, a “hard” signal

failure occurs instead of a pattern dependent error that may be very

infrequent and impossible to trouble-shoot.

minimize noise and may be externally decoupled separately or

simply tied together.

JTAG boundary scan pins are provided with signals TMS, TCK, TDI

and TDO. TMS and TCK are no-connects (no bond wires) and TDI

and TDO are shorted together internally. Boundary scan

functionality is not implemented at this time.