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FIN212ACGFX Datasheet(PDF) 9 Page - Fairchild Semiconductor |
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FIN212ACGFX Datasheet(HTML) 9 Page - Fairchild Semiconductor |
9 / 22 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN212AC Rev. 1.0.1 9 Application Diagrams (Continued) Figure 5. 8-Bit YUV 1.3MPixel CMOS Imager (Example Shows BGA 42-Pin Package) Serializer Configuration: PLL Frequency Mode: MODE 3 (S1=S0=1) 10-30MHz Frequency Range PLL Divide Mode: Standard Not Over-Clocked (PLL1=0, PLL0=1) Multiplier 7x Master Clock Bypass Mode: (clock passes from CKSI to CKP) Deserializer Configuration: Edge Rate Mode: Fast MODE 1 (S1=0, S0=1) Pulse Width Mode: Standard Non-Inverting, (PWS1=PWS0=0) Pulse Width; 3.5 x Serial CLK Period Master Clock Bypass Mode: Clock passes from STROBE to CKSO |
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