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FBL2031 Datasheet(PDF) 4 Page - NXP Semiconductors

Part No. FBL2031
Description  9-bit BTL 3.3V latched/registered/pass-thru Futurebus transceiver
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

FBL2031 Datasheet(HTML) 4 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
The TTL-level side (A port) has a common I/O. The common I/O,
open collector B port operates at BTL signal levels. The logic
element for data flow in each direction is controlled by two mode
select inputs (SEL0 and SEL1). A “00” configures latches in both
directions. A “10” configures thru mode in both directions. A “01”
configures register mode in both directions. A “11” configures
register mode in the A-to-B direction and latch mode in the B-to-A
When configured in the buffer mode, the inverse of the input data
appears at the output port. In the register mode, data is stored on
the rising edge of the appropriate clock input (LCAB or LCBA). In the
latch mode, clock pins serve as transparent-Low latch enables.
Regardless of the mode, data is inverted from input to output.
The 3-State A port is enabled by asserting a High level on OEA. The
B port has two output enables, OEB0 and OEB1. Only when OEB0
is High and OEB1 is Low is the output enabled.
When either OEB0 is Low or OEB1 is High, the B port is inactive
and is pulled to the level of the pull-up voltage. New data can be
entered in the register and latched modes or can be retained while
the associated outputs are in 3-State (A port) or inactive (B port).
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V.
The B-port interfaces to “Backplane Transceiver Logic” (see the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1V p-p, between 1V and 2V) and
reduced capacitive loading by placing an internal series diode on the
drivers. BTL also provides incident wave switching, a necessity for
high performance backplanes.
Output clamps are provided on the BTL outputs to further reduce
switching noise. The “VOH” clamp reduces inductive ringing effects
during a Low-to-High transition. The “VOH” clamp is always active.
The other clamp, the “trapped reflection” clamp, clamps out ringing
below the BTL 0.5V VOL level. This clamp remains active for
approximately 100ns after a High-to-Low transition.
To support live insertion, OEB0 is held Low during power on/off
cycles to insure glitch- free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
3.3V level while VCC is Low. The BIAS V pin is a low current input
which will reverse-bias the BTL driver series Schottky diode, and
also bias the B port output pins to a voltage between 1.62V and
2.1V. This bias function is in accordance with IEEE BTL Standard
1194.1. If live insertion is not a requirement, the BIAS V pin should
be tied to a VCC pin.
The LOGIC GND and BUS GND pins are isolated inside the
package to minimize noise coupling between the BTL and TTL
sides. These pins should be tied to a common ground external to the
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a “hard” signal
failure occurs instead of a pattern dependent error that may be
infrequent and impossible to troubleshoot.
As with any high power device, thermal considerations are critical. It
is recommended that airflow (300Ifpm) and/or thermal mounting be
used to ensure proper junction temperature.
Still air
300 Linear feet per minute air flow
Thermally mounted on one side to heat sink

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