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FBL2031 Datasheet(PDF) 3 Page - NXP Semiconductors

Part No. FBL2031
Description  9-bit BTL 3.3V latched/registered/pass-thru Futurebus transceiver
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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FBL2031 Datasheet(HTML) 3 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
3
PIN CONFIGURATION
52 51 50 49 48 47 46
45 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16 17 18 19
20 21
22 23 24 25 26
BUS GND
B1
BUS GND
B2
BUS GND
B3
BUS GND
B4
BUS GND
B5
BUS GND
B6
BUS GND
LOGIC GND
A2
A3
A4
LOGIC GND
A5
A6
A7
LOGIC GND
9-Bit latched/registered transceiver
FBL2031
52-lead PQFP
LOGIC GND
LOGIC GND
LOGIC GND
LOGIC GND
SG00087
PIN DESCRIPTION
SYMBOL
PIN NUMBER
TYPE
NAME AND FUNCTION
A0 – A8
50, 52, 2, 4, 6, 8, 10, 12, 14
I/O
BiCMOS data inputs/3-State outputs (TTL)
B0 – B8
40, 38, 36, 34, 32,
30, 28, 26, 24
I/O
Data inputs/Open Collector outputs, High current drive (BTL)
OEB0
46
Input
Enables the B outputs when High
OEB1
45
Input
Enables the B outputs when Low
OEA
47
Input
Enables the A outputs when High
BUS GND
25, 27, 29, 31, 33,
35, 37, 39, 41
GND
Bus ground (0V)
LOGIC GND
51, 1, 3, 5, 7, 9, 11, 13
GND
Logic ground (0V)
VCC
23, 43, 49
Power
Positive supply voltage
BIAS V
48
Power
Live insertion pre-bias pin
BG VCC
17
Power
Band Gap threshold voltage reference
BG GND
19
GND
Band Gap threshold voltage reference ground
SEL0
20
Input
Mode select
SEL1
15
Input
Mode select
LCAB
18
Input
A to B clock/latch enable (transparent latch when Low)
LCBA
16
Input
B to A clock/latch enable (transparent latch when Low)
TMS
42
Input
Test Mode Select (optional, if not implemented then no connect)
TCK
44
Input
Test Clock (optional, if not implemented then no connect)
TDI
22
Input
Test Data In (optional, if not implemented then no connect)
TDO
21
Output
Test Data Out (optional, if not implemented then shorted to TDI)


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