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FBL2031 Datasheet(PDF) 10 Page - NXP Semiconductors

Part No. FBL2031
Description  9-bit BTL 3.3V latched/registered/pass-thru Futurebus transceiver
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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FBL2031 Datasheet(HTML) 10 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
10
AC ELECTRICAL CHARACTERISTICS
A TO B
9
Ω LOAD SPECIFICATIONS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C,
VCC = 3.3V,
Tamb = –40 to +85°C,
VCC = 3.3V±10%,
UNIT
MIN
TYP
MAX
MIN
MAX
tPLH
tPHL
Propagation delay (thru latch)
An to Bn
Waveform 1, 2
1.4
1.3
2.6
2.5
3.8
3.8
1.0
1.0
4.9
4.2
ns
tPLH
tPHL
Propagation delay (transparent latch)
An to Bn
Waveform 1, 2
1.7
2.0
2.9
3.5
4.2
5.0
1.0
1.5
5.4
5.7
ns
tPLH
tPHL
Propagation delay
LCAB to Bn (latch)
Waveform 1, 2
8.8
8.4
11.6
11.0
14.5
13.7
6.7
6.7
17.9
16.6
ns
tPLH
tPHL
Propagation delay
LCAB to Bn (register)
Waveform 1, 2
2.3
2.5
3.6
4.0
5.0
5.4
1.4
1.9
6.2
6.4
ns
tPLH
tPHL
Propagation delay
SEL0 or SEL1 to Bn (inverting)
Waveform 1, 2
2.3
1.3
3.8
4.8
5.5
8.8
1.2
1.0
7.0
9.6
ns
tPLH
tPHL
Propagation delay
SEL0 or SEL1 to Bn (non-inverting)
Waveform 1, 2
2.0
2.6
4.4
4.3
7.2
6.1
1.1
1.7
8.5
7.6
ns
tPLH
tPHL
OEBn to Bn
Waveform 1, 2
1.2
1.9
2.9
3.3
4.8
4.7
1.0
1.2
5.8
6.4
ns
tTLH
tTHL
Output transition time, Bn Port
(1.3V to 1.8V)
Test Circuit and
Waveforms
1.2
0.4
3.0
1.5
ns
tSK(o)
Output to output skew for multiple
channels1
Waveform 3
0.4
1.0
2.0
ns
tSK(p)
Pulse skew2
 tPHL – tPLH MAX
Waveform 2
0.3
1.0
1.5
ns
NOTES:
1.
 tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or
HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). tSK (0) compares tPLH on a given path to tPLH
on any other path or compares tPHL on a given path to tPHL on any other path.
2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).


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