Micrel, Inc.

SY89844U

May 2005

M9999-050305

9

Case #2: Input Clock Failure:

Switching from a

selected clock stuck HIGH to a valid clock (RPE

enabled).

If CLK1 fails HIGH before the RPE MUX selects

CLK2 (using the SEL pin), the switchover will occur

in three stages.

• Stage 1: The output will remain HIGH for a

limited number of pulses of CLK2.

• Stage 2: The output will switch to LOW and then

remain LOW for a limited number of falling edges

of CLK2.

• Stage 3: The output will follow CLK2.

Timing Diagram 2

Note: Output shows extended clock cycle during switchover. Pulse width for both high and low of this cycle will always be

greater than 50% of the CLK2 period.