1

SY89834U

Micrel, Inc.

M9999-080505

hbwhelp@micrel.com or (408) 955-1690

DESCRIPTION

s Selects between two LVTTL/CMOS inputs and

provides 4 LVPECL output copies

s Guaranteed AC performance over temperature

and voltage:

• DC-to >1.0GHz throughput

• <500ps propagation delay (IN-to-Q)

• < 20ps within-device skew

• < 225ps rise/fall time

s Ultra-low jitter design:

• < 1ps

• < 1ps

• < 10ps

• < 10ps

s Low voltage 2.5V and 3.3V supply operation

s 100K LVPECL outputs

s Industrial temperature range: –40

s Includes a 2:1 MUX select input

s Accepts single-ended TTL/CMOS inputs and

provides four LVPECL outputs

s Available in 16-pin (3mm

××××× 3mm) MLF™ package

FEATURES

2.5V/3.3V TWO INPUT, 1GHz LVTTL/CMOS-

TO-LVPECL 1:4 FANOUT BUFFER/

TRANSLATOR WITH 2:1 INPUT MUX

SY89834U

APPLICATIONS

s Processor clock distribution/translation

s SONET clock distribution/translation

s Fibre Channel clock distribution/translation

s Gigabit Ethernet clock distribution/translation

s Single-ended ASIC-to-differential communication

IC signal translation

The SY89834U is a high-speed, 1GHz LVTTL/CMOS-to-

LVPECL fanout buffer/translator optimized for high-speed

ultra-low skew applications. The input stage is designed to

accept two single-ended LVTTL/CMOS compatible signals

that feed into a 2:1 MUX. The selected input is translated

and distributed as four differential 100K LVPECL outputs.

Within device skew is guaranteed to be less than 20ps over

supply voltage and temperature.

The single-ended input buffers accept TTL/CMOS logic

levels. The internal threshold of the buffers is defined as

The SY89834U is a part of Micrel's high-speed Precision

combination, consult Micrel's website at: www.micrel.com,

and choose from a comprehensive product line of high-

speed, low-skew fanout buffers, translators and clock

generators.

FUNCTIONAL BLOCK DIAGRAM

Precision Edge is a registered trademark of Micrel, Inc.

MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.

IN1

(LVTTL/CMOS)

(LVTTL/CMOS)

IN2

Q0

/Q0

Q1

/Q1

Q2

/Q2

Q3

/Q3

Q

D

EN

LVTTL/CMOS)

SEL

(LVTTL/CMOS)

1

0

MUX

1:4

August 2005