Electronic Components Datasheet Search |
|
SY89826LHYTR Datasheet(PDF) 1 Page - Micrel Semiconductor |
|
SY89826LHYTR Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 10 page 1 Precision Edge® SY89826L Micrel, Inc. M9999-011907 hbwhelp@micrel.com or (408) 955-1690 DESCRIPTION s High-performance, 1GHz LVDS fanout buffer/ translator s 22 differential LVDS output pairs s Guaranteed AC parameters over temperature and voltage: • > 1GHz fMAX • < 50ps within device skew • < 400ps tr /tf time s Low jitter performance • < 1ps (rms) cycle-to-cycle jitter • < 1ps (pk-pk) total jitter s 2:1 mux input accepts LVDS and LVPECL 3.3V supply voltage s LVDS input includes internal 100 Ω termination s Output enable function s Available in a 64-Pin EPAD-TQFP FEATURES 3.3V 1GHz PRECISION 1:22 LVDS FANOUT BUFFER/TRANSLATOR WITH 2:1 INPUT MUX Precision Edge® SY89826L APPLICATIONS s Enterprise networking s High-end servers s Communications 1 Rev.: D Amendment: /0 Issue Date: January 2007 The SY89826L is a precision fanout buffer with 22 differential LVDS (Low Voltage Differential Swing) output pairs. The part is designed for use in low voltage 3.3V applications that require a large number of outputs to drive precisely aligned, ultra low-skew signals to their destination. The input is multiplexed from either LVDS or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK_SEL pin. The OE (Output Enable) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The SY89826L features a low pin-to-pin skew of less than 50ps—performance previously unachievable in a standard product having such a high number of outputs. The SY89826L is available in a single space saving package, enabling a lower overall cost solution. OE(1) CLK_SEL Q0 – Q21 /Q0 – /Q21 0 0 LOW HIGH 0 1 LOW HIGH 1 0 LVDS_CLK /LVDS_CLK 1 1 LVPECL_CLK /LVPECL_CLK TRUTH TABLE NOTE: 1. The OE (output enable) signal is synchronized with the low level of the LVDS_CLK and LVPECL_CLK signal. FUNCTIONAL BLOCK DIAGRAM CLK_SEL LVPECL_CLK /LVPECL_CLK OE 0 1 22 22 Q0 - Q21 /Q0 - /Q21 LEN D Q LVDS_CLK /LVDS_CLK 100 Ω internal input termination 22 LVDS compatible outputs Precision Edge is a registered trademark of Micrel, Inc. Precision Edge® |
Similar Part No. - SY89826LHYTR |
|
Similar Description - SY89826LHYTR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |