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SY89826L Datasheet(PDF) 9 Page - Micrel Semiconductor |
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SY89826L Datasheet(HTML) 9 Page - Micrel Semiconductor |
9 / 10 page 9 Precision Edge® SY89826L Micrel, Inc. M9999-011907 hbwhelp@micrel.com or (408) 955-1690 DETAILED DESCRIPTION The SY89826L is a precision 1:22 fanout buffer. It accepts either an LVPECL or LVDS input, selectable by an input mux, and outputs 22 LVDS output pairs. The device features a synchronous output enable. The SY89826L provides extremely low skew across its outputs. LVPECL_CLK The SY89826L allows one input with standard LVPECL voltage swing. This input may be adjusted per the data sheet characteristics regarding the CMR and minimum input swing. As the SY89826L contains no appropriate internal termination, upstream devices need to be properly terminated to provide the proper LVPECL input swing. If not being used (CLK_SEL is LOW), this input pair may be left floating, as it is internally terminated to ground via a 75k Ω pull-down resistor. LVDS_CLK The SY89826L allows one input with standard LVDS voltage swing. The SY89826L provides an appropriate internal 100 Ω termination resistor. Hence, upstream LVDS devices do not require external termination to drive the SY89826L. If not being used (CLK_SEL is HIGH), this input pair may be left floating. CLK_SEL Input The CLK_SEL TTL Input is used to select either LVDS_CLK (CLK_SEL is LOW) or LVPECL_CLK (CLK_SEL is LOW),. OE The SY89826L's output enable function is designed to disable the outputs only when the outputs are LOW. This avoids the possibility of generating runt pulses. The OE input is an asynchronous input, but operates as a synchronous enable. For synchronous operation, please adhere to the specific setup and hold times. When disabled, the Q outputs are LOW and the /Q outputs are HIGH. LVDS Outputs The SY89826L's LVDS outputs swing typically 350mV around a 1.25V common mode voltage above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input is kept tight to keep EMI low. Each of the SY89826L's LVDS outputs should be terminated with a 100 Ω termination resistor including any unused output pairs. This ensures the best jitter and skew performance of the device. Part Number Function Data Sheet Link SY55855V Dual CML/PECL/LVPECL-to-LVDS www.micrel.com/product-info/products/sy55855v.shtml Translator SY89825U 2.5/3.3V 1:22 High-performance, www.micrel.com/product-info/products/sy89825u.shtml Low-voltage PECL Bus Clock Driver & Translator w/ Internal Termination SY89828L 3.3V 1GHz Dual 1:10 Precision www.micrel.com/product-info/products/sy89828l.shtml LVDS Fanout Buffer with 2:1 Input Mux SY89829U 2.5/3.3V High-performance, Dual 1:10 www.micrel.com/product-info/products/sy89829u.shtml LVPECL Clock Driver w/ Internal Termination & Redundant Switchover M-0317 HBW Solutions www.micrel.com/product-info/as/solutions.shtml Exposed Pad Amkor Exposed Pad Application Note www.amkor.com/products/notes_papers/epad.pdf RELATED PRODUCT AND SUPPORT DOCUMENTATION |
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