1

SY89808L

Micrel, Inc.

M9999-091405

hbwhelp@micrel.com or (408) 955-1690

FEATURES

power

offset voltage

temperature range

The SY89808L is a High-Performance Bus Clock Driver with

9 differential HSTL (High-Speed Transceiver Logic) 1.5V

compatible output pairs. The part is designed for use in low-

voltage (3.3V/1.8V) applications which require a large number

of outputs to drive precisely aligned, ultra-low skew signals to

their destination. The input is multiplexed from either HSTL or

LVPECL (Low-Voltage Positive-Emitter-Coupled Logic) by the

CLK_SEL pin.

The Output Enable (OE) is synchronous and triple-buffered

so that the outputs will only be enabled/disabled when they are

already in the LOW state. This avoids any potential of generating

a runt clock pulse when the device is enabled/disabled, as can

occur with an asynchronous control. The triple-buffering feature

provides a three-clock delay from the time the OE input is

asserted/de-asserted to when the clock appears at the outputs.

The SY89808L features an ultra-low pin-to-pin skew of less

than 25ps. The SY89808L is available in a 32-TQFP space

saving package, enabling a lower overall cost solution.

3.3V, 500MHz, 1:9 DIFFERENTIAL

HSTL (1.5V) FANOUT BUFFER/

TRANSLATOR

DESCRIPTION

SY89808L

LOGIC SYMBOL

APPLICATIONS

CLK_SEL

HSTL_CLK

/HSTL_CLK

LVPECL_CLK

/LVPECL_CLK

OE

0

1

9

9

Q0 — Q8

/Q0 — /Q8

EN

ENABLE

LOGIC

Rev.: E

Amendment: /0

Issue Date:

September 2005

TYPICAL PERFORMANCE

200

300

400

500

600

700

800

900

FREQUENCY (MHz)

Output Amplitude

vs. Frequency

Precision Edge is a registered trademark of Micrel, Inc.

TRUTH TABLE

CLK_SEL

0

0

LOW

HIGH

0

1

LOW

HIGH

1

0

HSTL_CLK

/HSTL_CLK

1

1

LVPECL_CLK

/LVPECL_CLK

Notes:

1. The OE (output enable) signal is synchronized with the low level of the

HSTL_CLK and LVPECL_CLK signal.