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SY89533LHCTR Datasheet(PDF) 3 Page - Micrel Semiconductor

Part # SY89533LHCTR
Description  3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND LVDS BUS CLOCK SYNTHESIZER
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

SY89533LHCTR Datasheet(HTML) 3 Page - Micrel Semiconductor

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3
Precision Edge®
SY89532/33L
Micrel, Inc.
M9999-110405
hbwhelp@micrel.com or (408) 955-1690
PIN DESCRIPTION
Pin Number
Pin Name
Functional Description
4
VCO_SEL
LVTTL/CMOS-Compatible Input: Selects between internal or external VCO. For
external VCO, leave floating. Default condition is logic HIGH. Internal 25k
pull-up.
When tied LOW, internal VCO is selected.
7
LOOP REF
Analog Input/Output: Provides the reference voltage for PLL loop filter.
8
LOOP FILTER
Analog Input/Output: Provides the loop filter for PLL. See “External Loop Filter
Considerations” for loop filter values.
13,14,15,16
M (3:0)
LVTTL/CMOS-Compatible Input: Used to change the PLL (Phase-Lock Loop)
feedback divider. Internal 25k
pull-up. (M0 = LSB). Default is logic HIGH.
See “Feedback Divide Select” table.
22, 23, 24
FSEL_C (2:0)
LVTTL/CMOS-Compatible Input: Bank C post divide select. Internal 25k
pull-up.
Default is logic HIGH. See “Post-Divide Frequency Select” table.
26, 27, 28
FSEL_B (2:0)
LVTTL/CMOS-Compatible Input: Bank B post divide select. Internal 25k
pull-up.
Default is logic HIGH. See “Post-Divide Frequency Select” table.
56, 57, 58
FSEL_A (2:0)
LVTTL/CMOS-Compatible Input: Bank A post divide select. Internal 25k
pull-up.
Default is logic HIGH. See “Post-Divide Frequency Select.” FSEL_A0 = LSB.
59
OUT_SYNC
Banks A,B,C output synchronous control: (LVTTL/CMOS compatible). Internal
25k
pull-up. After any bank has been programmed, toggle with a HIGH-LOW-
HIGH pulse to resynchronize all output banks.
Configuration
Pin Number
Pin Name
Functional Description
1, 2, 3
NC
No Connect: Leave floating.
10, 11
XTAL2, XTAL1
Crystal Input. Directly connect a series resonant crystal across inputs.
12
VBB_REF
Reference Output Voltage. Used for single-ended input. Maximum sink/source
current = 0.5mA.
5, 6
/EXT_VCO, EXT_VCO
Differential “Any In” Compatible Input Pair. Allows for external VCO connection. The “Any
In” input structure accepts many popular logic types. See “Input Interface for ExtVCO
Pins” section for intercace diagrams. Can leave unconnected if using internal VCO.
51, 52, 53, 54
QA1 to QA0
Bank A 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_A
(0:2). Terminate outputs with 50
Ω to V
CC –2V. See “Output Termination
Recommendations” section for termination detail.
32–49
QB8 to QB0
Bank B Output Drivers: SY89532: 100k LVPECL output drivers.
SY89533: Differential LVDS outputs. See “Output Termination Recommendations”
section for termination detail. Output frequency is controlled by FSEL_B (0:2).
17, 18, 19, 20
QC1 to QC0
Bank C 100k LVPECL Output Drivers: Output frequency is controlled by
FSEL_C (0:2). Terminate outputs with 50
Ω to V
CC–2V. See “Output Termination
Recommendations” section.
64
NC
No Connect: Leave floating.
Input/Output
Pin Number
Pin Name
Functional Description
60, 61
V
CC_Logic
Power for Core Logic: Connect to 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB.
62
V
CCA
Power for PLL: Connect to “quiet” 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB.
55
V
CCOA
Power for Output Drivers: Connect all V
CCO pins to 3.3V supply. VCCO pins are not
30, 31, 50
V
CCOB
connected internally on the die.
21
V
CCOC
9, 25, 63, 29
GND
Ground: Exposed pad must be soldered to a ground plane.
(exposed pad)
Power


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