Electronic Components Datasheet Search |
|
SY89464U Datasheet(PDF) 7 Page - Micrel Semiconductor |
|
SY89464U Datasheet(HTML) 7 Page - Micrel Semiconductor |
7 / 19 page Micrel, Inc. SY89464U December 2005 M9999-120105-B hbwhelp@micrel.com or (408) 955-1690 7 AC Electrical Characteristics(7) VCC = 2.5V ±5% or 3.3V ±10%; RL = 50Ω to VCC-2V; TA = –40°C to + 85°C, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units fMAX Maximum Operating Frequency VOUT ≥ 400mV 1.5 2.0 GHz Differential Propagation Delay In-to-Q 100mV < VIN ≤ 200mV (8) 550 800 1150 ps In-to-Q 200mV < VIN ≤ 800mV (8) 500 750 1100 ps SEL-to-Q RPE enabled, see Timing Diagram 17 cycles tpd SEL-to-Q RPE disabled (VSEL = VCC/2) 600 1200 ps tpd Tempco Differential Propagation Delay Temperature Coefficient 500 fs/ oC tS EN Set-up Time EN-to-CLK Note 9 0 ps tH EN Hold Time CLK-to-EN Note 9 650 ps Output-to-Output Skew Note 10 5 25 ps tSKEW Part-to-Part Skew Note 11 300 ps Clock Random Jitter Note 12 1 psRMS Cycle-to-Cycle Jitter Note 13 1 psRMS Total Jitter Note 14 10 psPP tJITTER Crosstalk-Induced Jitter Note 15 0.7 psRMS tr, tf Output Rise/Fall Time (20% to 80%) At full output swing. 70 220 ps Notes: 7. High-frequency AC-parameters are guaranteed by design and characterization. 8. Propagation delay is measured with input tr, tf ≤ 300ps (20% to 80%) and VIL ≥ 800mV. The propagation delay is function of the rise and fall times at IN. See “Typical Operating Characteristics” for details. 9. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold do not apply. 10. Output-to-Output skew is measured between two different outputs under identical transitions. 11. Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 12. Random Jitter is measured with a K28.7 character pattern, measured at <fMAX. 13. Cycle-to-Cycle Jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the output signal. 14. Total Jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10 12 output edges will deviate by more than the specified peak-to-peak jitter value. 15. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the inputs. |
Similar Part No. - SY89464U |
|
Similar Description - SY89464U |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |