11

SY89296U

Micrel, Inc.

M9999-072706

hbwhelp@micrel.com or (408) 955-1690

APPLICATIONS INFORMATION

For best performance, use good high frequency layout

short. Use multiple vias where possible. Also, use controlled

impedance transmission lines to interface with the SY89296U

data inputs and outputs.

The VBB pin is an internally generated reference and is

available for use only by the SY89296U. When unused, this

pin should be left unconnected. The two common uses for

bias inputs for AC-coupling applications.

is used to bias the unused input. Please refer to Figure 10.

The PECL signal driving the SY89296U may optionally be

inverted in this case.

in Figure 13, to re-bias IN and/or /IN. This ensures that

SY89296U inputs are within acceptable common mode

range.

limited to 0.5mA or less.

Setting D Input Logic Thresholds

In all designs where the SY89296U GND supply is at

zero volts, the D inputs can accommodate CMOS and TTL

level signals, as well as PECL or LVPECL. Figures 11, 12,

cases.

Cascading

Two or more SY89296U may be cascaded in order to

extend the range of delays permitted. Each additional

SY89296U adds about 3.2ns to the minimum delay and

adds another 10240ps to the delay range.

Internal cascade circuitry has been included in the

SY89296U. Using this internal circuitry, the SY89296U may

be cascaded without any external gating.

Examples of cascading 2, 3, or 4 SY89296U appear in

Figures 7, 8, and 9.

IN

/IN

Q

/Q

IN

/IN

Q

FTUNE

FTUNE

/Q

D[9:0]

#1

#2

SETMIN

SETMAX

/CASCADE

CASCADE

D[10]

C[9:0]

C[10]

Control Word (11bits)

DAC

Figure 7. Cascading Two SY89296U

IN

/IN

Q

/Q

IN

/IN

Q

/Q

#1

#2

SETMIN

SETMAX

SETMIN

SETMAX

/CASCADE

CASCADE

D[10]

C[11]

IN

/IN

Q

FTUNE

FTUNE

/Q

D[9:0]

#3

/CASCADE

CASCADE

D[10]

C[9:0]

C[10]

Control Word (12bits)

DAC

Figure 8. Cascading Three SY89296U