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SY89296UTITR Datasheet(PDF) 7 Page - Micrel Semiconductor |
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SY89296UTITR Datasheet(HTML) 7 Page - Micrel Semiconductor |
7 / 15 page 7 Precision Edge® SY89296U Micrel, Inc. M9999-072706 hbwhelp@micrel.com or (408) 955-1690 TA = –40°C to +85°C; unless otherwise stated. Symbol Parameter Condition Min Typ Max Units fMAX Maximum Operating Frequency Clock 1.5 GHz tpd Propagation Delay IN to Q; D[0–10]=0 3200 4200 ps IN to Q; D[0–10]=1023 11500 14800 ps /EN to Q: D[0–10]=0 3400 4400 ps D10 to CASCADE 350 670 ps tRANGE Programmable Range tpd (max) – tpd (min) 8300 ps tSKEW Duty Cycle Skew tPHL – tPLH Note 8 25 ps ∆t Step Delay D0 High 10 ps D1 High 15 ps D2 High 35 ps D3 High 70 ps D4 High 145 ps D5 High 290 ps D6 High 575 ps D7 High 1150 ps D8 High 2300 ps D9 High 4610 ps D0-D9 High 9220 ps INL Integral Non-Linearity Note 9 –10 +10 %LSB tS Setup Time D t+o LEN 200 ps D to IN Note 10 350 ps /EN to IN Note 11 300 ps tH Hold Time LEN to D 200 ps IN to /EN Note 12 400 ps tR Release Time /EN to IN 500 ps SETMAX to LEN 500 ps SETMIN to LEN 450 ps tJITTER Cycle-to-Cycle Jitter Note 13 2psRMS Total Jitter Note 14 10 psPP Random Jitter Note 15 1psRMS tr, tf Output Rise/Fall Time 20% to 80% (Q) 50 85 160 ps 20% to 80% (CASCADE) 90 300 ps Duty Cycle 45 55 % fT FTUNE 0 ≤ FTUNE ≤ 1.25V 47 52 ps/V Notes: 7. High frequency AC electricals are guaranteed by design and characterization 8. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the crosspoint of the output. 9. INL (Integral Non-Linearity) is defined from its corresponding point on the ideal delay versus D[9:0] curve as the deviation from its ideal delay. The maximum difference is the INL. Theoretical Ideal Linearity (TIL) = (measured maximum delay – measured minimum delay) ÷ 1024. INL = measured delay – measured minimum delay + (step number × TIL). 10. This setup time defines the amount of time prior to the input signal. The delay tap of the device must be set. 11. This setup time defines the amount of the time that /EN must be asserted prior to the next transition of IN, /IN to prevent an output response greater than ±75mV to the IN, /IN transition. 12. Hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response greater than ±75mV to that IN, /IN transition. 13. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc = Tn – Tn+1, where T is the time between rising edges of the output signal. 14. Total jitter definition: with an ideal clock input, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to- peak jitter value. 15. Random jitter definition: jitter that is characterized by a Gaussian distribution, unbounded and is quantified by its standard deviation and mean. Random jitter is measured with a K28.7 comma defect pattern, measured at 1.5Gbps. AC ELECTRICAL CHARACTERISTICS(7) |
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