7

SY89295U

Micrel, Inc.

M9999-011806

hbwhelp@micrel.com or (408) 955-1690

Symbol

Parameter

Condition

Min

Typ

Max

Units

Maximum Operating Frequency

Clock

≥ 400mV

1.5

GHz

Propagation Delay

IN to Q; D[0–10]=0

3200

4200

ps

IN to Q; D[0–10]=1023

11500

14800

ps

/EN to Q: D[0–10]=0

3400

4400

ps

D10 to CASCADE

350

670

ps

Programmable Range

8300

ps

Duty Cycle Skew

Note 8

25

ps

∆t

Step Delay

D0 High

10

ps

D1 High

15

ps

D2 High

35

ps

D3 High

70

ps

D4 High

145

ps

D5 High

290

ps

D6 High

575

ps

D7 High

1150

ps

D8 High

2300

ps

D9 High

4610

ps

D0-D9 High

9220

ps

INL

Integral Non-Linearity

Note 9

–10

+10

%LSB

Setup Time

D to LEN

200

ps

D to IN

Note 10

350

ps

/EN to IN

Note 11

300

ps

Hold Time

LEN to D

200

ps

IN to /EN

Note 12

400

ps

Release Time

/EN to IN

500

ps

SETMAX to LEN

500

ps

SETMIN to LEN

450

ps

Cycle-to-Cycle Jitter

Note 13

Total Jitter

Note 14

10

Random Jitter

Note 15

Output Rise/Fall Time

20% to 80% (Q)

50

85

160

ps

20% to 80% (CASCADE)

90

300

ps

Duty Cycle

45

55

%

Notes:

7. High frequency AC electricals are guaranteed by design and characterization.

8. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the crosspoint of the output.

9. INL (Integral Non-Linearity) is defined from its corresponding point on the ideal delay versus D[9:0] curve as the deviation from its ideal delay. The

maximum difference is the INL. Theoretical Ideal Linearity (TIL) = (measured maximum delay – measured minimum delay)

÷ 1024. INL = measured

delay – measured minimum delay + (step number

× TIL).

10. This setup time defines the amount of time prior to the input signal. The delay tap of the device must be set.

11. This setup time defines the amount of the time that /EN must be asserted prior to the next transition of IN, /IN to prevent an output response greater

than

±75mV to the IN, /IN transition.

12. Hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response greater

than

±75mV to the IN, /IN transition.

13. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles over a random sample of adjacent cycle pairs.

peak jitter value.

15. Random jitter definition: Jitter that is characterized by a Gaussian distribution, unbounded and is quantified by its standard deviation and mean.

Random jitter is measured with a K28.7 comma defect pattern, measured at 1.5Gbps.