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SY88933V Datasheet(PDF) 5 Page - Micrel Semiconductor

Part No. SY88933V
Description  3.3V/5V 1.25Gbps PECL LOW-POWER LIMITING POST AMPLIFIER WITH TTL SIGNAL DETECT
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

SY88933V Datasheet(HTML) 5 Page - Micrel Semiconductor

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5
SY88933V
Micrel, Inc.
M9999-031506
hbwhelp@micrel.com or (408) 955-1690
DETAILED DESCRIPTION
The SY88933V low-power limiting post amplifier
operates from a single +3.3V or +5V power supply, over
temperatures from –40
°C to +85°C. Signals with data
rates up to 1.25Gbps and as small as 5mVp-p can be
amplified. Figure 1 shows the allowed input voltage swing.
The SY88933V generates an SD output. SD
LVL sets the
sensitivity of the input amplitude detection.
Input Amplifier/Buffer
Figure 2 shows a simplified schematic of the
SY88933V's input stage. The high-sensitivity of the input
amplifier allows signals as small as 5mV
PP to be detected
and amplified. The input amplifier allows input signals as
large
as
1800mV
PP. Input signals are linearly amplified with a
typically 38dB differential voltage gain. Since it is a limiting
amplifier, the SY88933V outputs typically 1500mV
PP
voltage-limited waveforms for input signals that are
greater than 18mV
PP. Applications requiring the
SY88933V to operate with high-gain should have the
upstream TIA placed as close as possible to the
SY88933V’s input pins to ensure the best performance
of the device.
Output Buffer
The SY88933V’s PECL output buffer is designed to
drive 50
Ω lines. The output buffer requires appropriate
termination for proper operation. An external 50
Ω resistor
to V
CC–2V for each output pin provides this. Figure 3
shows a simplified schematic of the output stage and
includes an appropriate termination method.
Signal-Detect
The SY88933V generates a chatter-free SD open-
collector TTL output with internal 6.75k
Ω pullup resistor
as shown in Figure 4. SD is used to determine that the
input amplitude is large enough to be considered a valid
input. SD asserts high if the input amplitude rises above
the threshold set by SD
LVL and deasserts low otherwise.
SD can be fed back to the enable (EN) input to maintain
output stability under a loss of signal condition. EN
deasserts the true output signal without removing the
input signals. Typically, 4.6dB SD hysteresis is provided
to prevent chattering.
Signal-Detect Level Set
A programmable SD level set pin (SDLVL) sets the
threshold of the input amplitude detection. Connecting
an external resistor between V
CC and SDLVL sets the
voltage at SD
LVL. This voltages ranges from VCC to VREF.
The external resistor creates a voltage divider between
V
CC and VREF as shown in Figure 5. If desired, an
appropriate external voltage may be applied rather than
using a resistor. The smaller the external resistor, implying
a smaller voltage difference from SD
LVL to VCC, the
smaller the SD sensitivity. Hence, larger input amplitude
is
required
to
assert
SD.
“Typical
Operating
Characteristics” shows the relationship between the input
amplitude detection sensitivity and the SDLVL voltage.
Hysteresis
The SY88933V provides typically 4.6dB SD electrical
hysteresis. By definition, a power ratio measured in dB
is 10log(power ratio). Power is calculated as V2
IN/R for
an electrical signal. Hence, the same ratio can be stated
as 20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and
hence the ratios change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB
given in the datasheet. The SY88933V provides typically
2.3dB SD optical hysteresis. As the SY88933V is an
electrical device, this datasheet refers to hysteresis in
electrical terms. With 6dB SD hysteresis, a voltage factor
of two is required to assert or deassert SD.


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