Electronic Components Datasheet Search |
|
SY88149CLKGTR Datasheet(PDF) 7 Page - Micrel Semiconductor |
|
SY88149CLKGTR Datasheet(HTML) 7 Page - Micrel Semiconductor |
7 / 10 page Micrel, Inc. SY88149CL February 2007 7 M9999-021207-B hbwhelp@micrel.com or (408) 955-1690 Functional Block Diagram Detailed Description The SY88149CL high-sensitivity limiting post amplifier operates from a single +3.3V power supply, over temperatures from –40°C to +85°C. Signals with data rates up to 1.25Gbps and as small as 5mVPP can be amplified. Figure 1 shows the allowed input voltage swing. The SY88149CL generates an SD output, allowing feedback to EN for output stability. SDLVL sets the sensitivity of the input amplitude detection. Input Amplifier/Buffer Figure 2 shows a simplified schematic of the input stage. The high-sensitivity of the input amplifier allows signals as small as 5mVPP to be detected and amplified. The input amplifier allows input signals as large as 1800mVPP. Input signals are linearly amplified with a typically 42dB differential voltage gain. Since it is a limiting amplifier, the SY88149CL outputs typically 1500mVPP voltage-limited waveforms for input signals that are greater than 12mVPP. Applications requiring the SY88149CL to operate with high-gain should have the upstream TIA placed as close as possible to the SY88149CL’s input pins. This ensures the best performance of the device. Output Buffer The SY88149CL’s PECL output buffer is designed to drive 50Ω lines. The output buffer requires appropriate termination for proper operation. An external 50Ω resistor to VCC–2V for each output pin provides this. Figure 3 shows a simplified schematic of the output stage. Signal Detect The SY88149CL generates a chatter-free Signal-Detect (SD) open-collector TTL output with internal 4.75kΩ pull- up resistor, as shown in Figure 4. SD is used to determine that the input amplitude is too small to be considered a valid input. SD asserts high if the input amplitude rises above threshold set by SDLVL and de- asserts low otherwise. SD can be fed back to the enable (EN) input to maintain output stability under a SDs of signal condition. EN de-asserts low the true output signal without removing the input signals. Typically, 3.4dB SD hysteresis is provided to prevent chattering. Signal Detect Level Set A programmable SD level set pin (SDLVL) sets the threshold of the input amplitude detection. Connecting an external resistor between VCC and SDLVL sets the voltage at SDLVL. This voltage ranges from VCC to VREF. The external resistor creates a voltage divider between VCC and VREF, as shown in Figure 5. Hysteresis The SY88149CL provides typically 3.4dB SD electrical hysteresis. By definition, a power ratio measured in dB is 10log (power ratio). Power is calculated as V 2 IN/R for an electrical signal. Hence the same ratio can be stated as 20log (voltage ratio). While in linear mode, the electrical voltage input changes linearly with the optical power and hence the ratios change linearly. Therefore, the optical hysteresis in dB is half the electrical hysteresis in dB given in the data sheet. The SY88149CL is an electrical device; this data sheet refers to hysteresis in electrical terms. With 3.4dB SD hysteresis, a voltage factor of 1.5 is required to assert or de-assert SD. |
Similar Part No. - SY88149CLKGTR |
|
Similar Description - SY88149CLKGTR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |