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SY87739LHYTR Datasheet(PDF) 8 Page - Micrel Semiconductor |
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SY87739LHYTR Datasheet(HTML) 8 Page - Micrel Semiconductor |
8 / 13 page 8 SY87739L Micrel, Inc. M9999-111406 hbwhelp@micrel.com or (408) 955-1690 the same coarse adjustment voltage, and so both center nominally at the same frequency. An 8-bit counter implements the voltage steps. The acquisition sequencer steps through this counter, which changes its voltage by about 12mV per step. The coarse input to the VCO is nominally set at 500MHz per Volt. The acquisition sequencer exercises the center frequency trim circuit so that the VCO control voltage ends up within about 12mV of where it should be, were it exactly centered for the desired output frequency. Lock Detector The SY87739L ensures proper operation of both synthesizers by verifying that both PLL have achieved lock. The LOCKED output asserts active high only when this is the case, that is, both PLL are locked. The SY87739L implements a digital lock detector that is both simple and robust. Each phase-frequency detector provides a charge pump output that is the logical OR of pump up and pump down pulses. The lock detect circuit processes this charge pump output with a pulse width discriminator. Once each reference clock rising edge, the discriminator will produce a pulse, only if the phase difference between the feedback divider and the reference input is too large. These pulses are subsequently processed digitally. A PLL that is out of lock, is declared to be in lock only if 256 consecutive reference clocks have NO large phase errors, as reported by the pulse width discriminator. Any large phase error event, even a single one, that arrives before lock is declared, will reset the circuit. Once in lock, a PLL is declared out of lock if more large- phase-difference than small-phase-difference events occur that is, if over time, a net of 256 large-phase-difference events occur. That is accomplished by counting up when large-phase-difference events occur and counting down in the case of small-phase events. Wrapper Synthesizer The frequency generated by the fractional-N PLL is further processed by a more classical PLL circuit, as shown in Figure 3. Phase- Frequency Detector/ Charge Pump VCO ÷M ÷N Loop Filter Output Frequency (fWROUT) Input Frequency (fFNOUT) Figure 3. Wrapper Architecture This circuit further modifies the frequency generated by the fractional-N loop. This comes in handy where digital wrapper and/or FEC is implemented. The wrapper synthesizer generates just a few ratios near 1. The wrapper modifies the frequency based on the values of M and N, the dividers, as per: 540MHz f N M f N M P± Q QQ WROUT FNOUT P±1 P±1 P ≤ =× =× + × ≤ f 729MHz REF Wrapper Phase-Frequency Detector This circuit generates pump up and pump down signals for the charge pump, and also generates delta phase for the lock detector. Wrapper Charge Pump This circuit converts the pump signals from the phase- frequency detector into current pulses. Charge pump current is fixed at about 20µA. An external loop filter integrates these current pulses into a control voltage. Wrapper VCO This circuit matches the fractional-N VCO in construction and operation, so that the center frequency trim circuit can center both the fractional-N VCO and the wrapper VCO at about the same frequency. Wrapper M Divider This circuit forms the denominator of the ratio by which the wrapper synthesizer modifies the fractional-N output frequency. The division ratio is selected via MicroWire™, as the 3-bit MdivSel register, as per Table 3 . MdivSel2 MdivSel1 MdivSel0 Divisor 000 16 001 16 010 18 011 17 100 31 101 14 110 32 111 15 Table 3. MdivSel Divisor Control The divisors are in two sets. The first set consists of the divisors 14, 15, 16, 17, and 18. The second set consists of 31 and 32. Both M and N must be chosen from the same set. For example, an N divisor of 31 and an M divisor of 17 results in undefined behavior. The N M ratio must be kept smaller than 17 14 , that is, 18 14 is not allowed. Wrapper N Divider This circuit forms the numerator of the ratio by which the wrapper synthesizer modifies the fractional-N output frequency. The division ratio is selected via MicroWire™, as the 3-bit NdivSel register, as per Table 4. |
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