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SY87813L Datasheet(PDF) 3 Page - Micrel Semiconductor |
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SY87813L Datasheet(HTML) 3 Page - Micrel Semiconductor |
3 / 15 page Micrel, Inc. SY87813L November 2006 3 M9999-112806-B hbwhelp@micrel.com or (408) 955-1690 Pin Description Pin Number Pin Name Pin Name 1 REFCLKSEL REFCLK Select (TTL Input). This input selects the single-ended TTL REFCLK input or the differential PECL REFCLKP/REFCLKN inputs. REFCLKSEL = HIGH selects PECL inputs. 2 3 RDINP, RDINN Serial Data Input. Differential PECL: These built-in line receiver inputs are connected to the differential receive serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data (RDOUT) information. The incoming data rate can be within one of eight frequency ranges depending upon the state of the FREQSEL pins. See “Frequency Selection” Table. 4 6 7 FREQSEL1 FREQSEL2 FREQSEL3 Frequency Select. TTL Inputs: These inputs select the output clock frequency range as shown in the “Frequency Selection” Table. 5 28 29 REFCLK, REFCLKP, REFCLKN Reference Clock. (Input): These inputs are used as the reference for the internal frequency synthesizer and the “training” frequency for the receiver PLL to keep it centered in the absence of data coming in on the RDIN inputs. REFCLK is single-ended TTL and REFCLKP and REFCLKN are differential PECL inputs selected by the REFCLKSEL pin 26 CD Carrier Detect. PECL Input: This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH, the input data stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be internally forced to a constant LOW, the data outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW and the clock recovery PLL forced to lock onto the clock frequency generated from REFCLK. 8 NC No connect. 9 10 PLLSP PLLSN Clock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis PLL. 11 GNDA Analog Ground. 12, 13 GND Ground. Ground pin and exposed pad must be connected to the same ground plane. 15 14 PLLRP PLLRN Clock Recovery PLL Loop Filter. External loop filter pins for the receiver PLL. 16 TCLKSEL Clock Select. TTL Input: This input is used to select either the recovered clock of the receiver PLL (TCLKSEL = HIGH) or the clock of the frequency synthesizer (TCLKSEL = LOW) to the TCLK outputs. 18 17 TCLKP, TCLKN Clock Output (Differential PECL): The PECL 100k outputs represent either the recovered clock (TCLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the frequency synthesizer (TCLKSEL = LOW). These outputs must be terminated with 50Ω to VCC-2V or equivalent. This applies even if these outputs are not used. 19, 22 VCCO Output Supply Voltage. Bypass with 0.1µF//0.01µF low ESR capacitors as close to VCC pins as possible. (1) 21 20 RCLKP, RCLKN Clock Output (Differential PECL): These PECL 100k outputs represent the recovered clock used to sample the recovered data (RDOUT). 24 23 RDOUTP RDOUTN Receive Data Output (Differential PECL): These PECL 100k outputs represent the recovered data from the input data stream (RDIN). This recovered data is specified against the rising edge of RCLK. These outputs must be terminated with 50Ω to VCC-2V or equivalent. This applies even if these outputs are not used. 32 25 DIVSEL1 DIVSEL2 Divider Select. TTL Inputs: These inputs select the ratio between the output clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in the “Reference Frequency Selection” Table. Note: 1. VCC, VCCA, VCCO must be the same value. |
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